PIC16F1934-E/ML Microchip Technology, PIC16F1934-E/ML Datasheet - Page 2

• Manufacturer Part Number: PIC16F1934-E/ML
• Description: IC PIC MCU FLASH 256KX7 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1934-E/ML

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART/MI2C/SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 1:
The core registers in the enhanced PIC12/16 are the
same as the legacy registers with the addition of a
second FSR/INDF, the BSR and mapping the W
register in WREG. The IRP, RP0 and RP1 bits are no
longer present in the STATUS because the BSR is now
available and the FSRs are now 16 bits wide.
TABLE 2:
These instructions were designed to fit inside the
“holes” in the existing 14-bit instruction word. By fitting
the existing memory design, the cost of the enhanced
devices was kept similar to the existing PIC12/16,
simplifying the decision to use the new features.
DS41375A-page 2
Note 1: All cycle counts increase by 1 if the file address points to INDF (0 or 1) and FSR points to program
Address
LSLF/ASRF
Mnemonic
0x0A
0x0B
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
ADDFSR
ADDWFC
SUBWFB
CALLW
MOVLB
MOVLP
MOVIW
MOVWI
RESET
ASRF
LSRF
BRA
BRW
memory.
SFR ADDRESSES
NEW INSTRUCTIONS
Operands
Register
PCLATH
INTCON
STATUS
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
BSR
PCL
f,d
f,d
f,d
f,d
f,d
k
k
k
k
*
*
-
-
-
Subtract W from F with Borrow
Move Literal to PCLATH
Add W and F with Carry
Branch Relative with W
Arithmetic Shift Right
Call Absolute with W
Move Literal to BSR
Add literal to FSRn
Logical Shift Right
Move INDFn to W
Move W to INDFn
Logical Shift Left
Branch Relative
Description
CPU Reset
Indirect Address for INDF0, High Byte
Indirect Address for INDF1, High Byte
Indirect Address for INDF0, Low Byte
Indirect Address for INDF1, Low Byte
Program Counter High Byte Latch
New Instructions
The new instructions improve arithmetic, simplify
paging and banking, and extend the capabilities of the
indirect addressing modes.
Interrupt Control Register
Indirect File Register 0
Indirect File Register 1
Program Counter Low
Bank Select Register
ALU Status Register
Description
W Register
© 2009 Microchip Technology Inc.
Cycles
1
1
1
1
2
2
2
1
1
1
1
1
1
1
(1)
Affected
C,DC,Z
C,DC,Z
C,DC,Z
Status
—
—
—
—
—
—
—
C
C
C
Z