ATTINY24A-SSU Atmel, ATTINY24A-SSU Datasheet - Page 129

• Manufacturer Part Number: ATTINY24A-SSU
• Description: MCU AVR 2K FLASH 20MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-SSU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 20 Channel
• For Use With: ATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2
15.2.1
8183C–AVR–03/11
Register Description
ACSR – Analog Comparator Control and Status Register
15-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the analog
comparator.
Table 15-1.
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed, internal bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog
Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
Bit
0x08 (0x28)
Read/Write
Initial Value
ACME
0
1
1
1
1
1
1
1
1
1
Analog Comparator Multiplexed Input
ACD
R/W
ADEN
0
7
X
1
0
0
0
0
0
0
0
0
ACBG
R/W
0
6
MUX[4:0]
XXXXX
XXXXX
00000
00001
00010
00011
00100
00101
00110
00111
ACO
N/A
R
5
Analog Comparator Negative Input
AIN1
AIN1
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
R/W
ACI
4
0
ACIE
R/W
3
0
ATtiny24A/44A/84A
ACIC
R/W
2
0
ACIS1
R/W
1
0
ACIS0
R/W
0
0
ACSR
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