ATMEGA88A-AUR Atmel, ATMEGA88A-AUR Datasheet - Page 217
![IC MCU AVR 8K FLASH 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA88A-AUR
Manufacturer Part Number
ATMEGA88A-AUR
Description
IC MCU AVR 8K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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21.3
21.3.1
21.3.2
8271C–AVR–08/10
Data Transfer and Frame Format
Transferring Bits
START and STOP Conditions
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 21-2. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signalled by changing the level of the SDA
line when the SCL line is high.
Figure 21-3. START, REPEATED START and STOP conditions
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
SDA
SCL
START
SDA
SCL
Data Stable
STOP
Data Change
START
Data Stable
REPEATED START
STOP
217
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