PIC12CE519-04/P Microchip Technology, PIC12CE519-04/P Datasheet - Page 326
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PIC12CE519-04/P
Manufacturer Part Number
PIC12CE519-04/P
Description
IC MCU OTP 1KX12 W/EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE519-04/P
Program Memory Type
OTP
Program Memory Size
1.5KB (1K x 12)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Eeprom Size
16 x 8
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
1
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE519-04/P
Manufacturer:
Microchip
Quantity:
710
Part Number:
PIC12CE519-04/P
Manufacturer:
MIC
Quantity:
20 000
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 326 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.18.1 Bus Collision During a START Condition
DS31017A-page 17-50
During a START condition, a bus collision occurs if:
a)
b)
During a START condition both the SDA and the SCL pins are monitored.
If:
then:
The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sam-
pled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the
SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that
another master is attempting to drive a data '1' during the START condition.
If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted
early
the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and
during this time, if the SCL pins is sampled as '0', a bus collision does not occur. At the end of
the BRG count the SCL pin is asserted low.
Note:
SDA or SCL are sampled low at the beginning of the START condition
SCL is sampled low before SDA is asserted low
the SDA pin is already low
or the SCL pin is already low,
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure
The reason that bus collision is not a factor during a START condition is that no two
bus masters can assert a START condition at the exact same time. Therefore, one
master will always assert SDA before the other. This condition does not cause a bus
collision because the two masters must be allowed to arbitrate the first address fol-
lowing the START condition, and if the address is the same, arbitration must be
allowed to continue into the data portion, Repeated Start, or STOP conditions.
17-37). If however a '1' is sampled on the SDA pin, the SDA pin is asserted low at
Preliminary
(Figure
(Figure
17-35).
17-36).
1997 Microchip Technology Inc.
(Figure
17-35).
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