PIC16LF1826-I/P Microchip Technology, PIC16LF1826-I/P Datasheet - Page 287
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PIC16LF1826-I/P
Manufacturer Part Number
PIC16LF1826-I/P
Description
IC MCU 8BIT FLASH 18-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1826-I/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16LF
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
3
Interface
EUSART, I2C, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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25.0
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
communications with peripheral systems, such as CRT
terminals
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 25-1:
© 2009 Microchip Technology Inc.
BRG16
Baud Rate Generator
SPBRGH
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
and
Full-Duplex
SPBRGL
personal
+ 1
EUSART TRANSMIT BLOCK DIAGRAM
F
Multiplier
OSC
BRG16
mode
SYNC
BRGH
computers.
TXEN
1 X 0 0
X 1 1 0
X 1 0 1
÷ n
x4
is
n
x16 x64
useful
Half-Duplex
0
0
0
MSb
(8)
Preliminary
for
Transmit Shift Register (TSR)
TX9D
TXREG Register
• • •
TX9
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 25-1 and Figure 25-2.
modes
8
Data Bus
PIC16F/LF1826/27
TRMT
LSb
0
TXIF
TXIE
Pin Buffer
and Control
SPEN
DS41391B-page 287
Interrupt
TX/CK pin
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