AT89LP428-20JU Atmel, AT89LP428-20JU Datasheet - Page 38
AT89LP428-20JU
Manufacturer Part Number
AT89LP428-20JU
Description
MCU 8051 4K FLASH SPI 32PLCC
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP428-20AU.pdf
(149 pages)
Specifications of AT89LP428-20JU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-PLCC
Processor Series
AT89x
Core
8051
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.1.4
10.2
38
Port 2 Analog Functions
AT89LP428/828
Push-pull Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. The push-pull port configuration is shown in
Figure 10-5. Push-pull Output
The AT89LP428/828 incorporates two analog comparators. In order to give the best analog per-
formance and minimize power consumption, pins that are being used for analog functions must
have both their digital outputs and inputs disabled. Digital outputs are disabled by putting the
port pins into the input-only mode as described in
on P2.4, P2.5, P2.6 and P2.7 are disabled whenever an analog comparator is enabled by setting
the CENA or CENB bits in ACSRA and ACSRB and that pin is configured for input-only mode.
To use an analog input pin as a high-impedance digital input while a comparator is enabled, that
pin should be configured in open-drain mode and the corresponding port register bit should be
set to 1. The analog input pins will always default to input-only mode after reset regardless of the
state of the Tristate-Port User Fuse.
If analog noise immunity is a concern, the P2.4–7 pins should not be used as high speed digital
inputs or outputs while the comparators are enabled.
From Port
Register
Input
Data
PWD
“Port Configuration” on page
V
CC
Figure
10-5.
Port
Pin
35. Digital inputs
3654A–MICRO–8/09
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