PIC12F675-E/MF Microchip Technology, PIC12F675-E/MF Datasheet - Page 30
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PIC12F675-E/MF
Manufacturer Part Number
PIC12F675-E/MF
Description
IC MCU CMOS 1K FLASH W/AD 8-DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F675-E/MF
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DFN
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 53270-913
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
4 bit
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
PIC12F629/675
4.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2T
REGISTER 4-1:
DS41190G-page 30
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1
GPPU
Using Timer0 with an External
Clock
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CK pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
PS2:PS0: Prescaler Rate Select bits
INTEDG
R/W-1
OPTION_REG: OPTION REGISTER (ADDRESS: 81h)
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
W = Writable bit
‘1’ = Bit is set
R/W-1
T0CS
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
OSC
R/W-1
T0SE
(and
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
a small RC delay of 20 ns) and low for at least 2T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
PSA
Note:
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
R/W-1
PS2
2010 Microchip Technology Inc.
x = Bit is unknown
R/W-1
PS1
R/W-1
PS0
bit 0
OSC