ATMEGA48PA-AU Atmel, ATMEGA48PA-AU Datasheet - Page 313
ATMEGA48PA-AU
Manufacturer Part Number
ATMEGA48PA-AU
Description
MCU AVR 4KB FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA48A-PU.pdf
(566 pages)
2.ATMEGA48A-PU.pdf
(33 pages)
3.ATMEGA48PA-MMH.pdf
(26 pages)
Specifications of ATMEGA48PA-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 6 Channel
Data Rom Size
256 B
Height
1 mm
Length
7 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
7 mm
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
1 000
Company:
Part Number:
ATMEGA48PA-AU
Manufacturer:
Atmel
Quantity:
900
Part Number:
ATMEGA48PA-AU
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
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ATMEL
Quantity:
723
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27.8.3
Table 27-19. Serial Programming Instruction Set (Hexadecimal values)
8271C–AVR–08/10
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Read Extended Fuse Bits
Serial Programming Instruction set
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Table 27-18. Typical Wait Delay Before Writing the Next Flash or EEPROM Location
Table 27-19 on page 313
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
(1)
Symbol
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
not used, the used must wait at least t
27-18). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
tent at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
power off.
Byte 1
$AC
$AC
$4D
$C1
$A0
$F0
$48
$40
$28
$20
$58
$30
$50
$58
$50
and
Figure 27-8 on page 315
0000 00aa
WD_EEPROM
adr MSB
adr MSB
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$00
$00
$08
$08
Instruction Format
before issuing the next byte (See
describes the Instruction set.
Extended adr
0000 000aa
0000 000aa
aaaa aaaa
Minimum Wait Delay
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
$00
$00
$00
$00
$00
$00
$00
4.5 ms
3.6 ms
9.0 ms
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
Byte4
$00
$00
$00
Table
313
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