PIC16F1823-I/P Microchip Technology, PIC16F1823-I/P Datasheet - Page 272
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F1823-I/P
Manufacturer Part Number
PIC16F1823-I/P
Description
IC MCU 8BIT FLASH 14-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC12F1822T-ISN.pdf
(404 pages)
3.PIC12F1822T-ISN.pdf
(10 pages)
4.PIC12F1822-IP.pdf
(6 pages)
Specifications of PIC16F1823-I/P
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
14-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 KB
Interface Type
MI2C, SPI, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F1823-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC12F1822T-ISN PDF datasheet #2
- PIC12F1822T-ISN PDF datasheet #3
- PIC12F1822-IP PDF datasheet #4
- Current page: 272 of 404
- Download datasheet (4Mb)
PIC12F/LF1822/PIC16F/LF1823
FIGURE 25-31:
25.6.10
While in Sleep mode, the I
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP1 interrupt is enabled).
25.6.11
A Reset disables the MSSP1 module and terminates
the current transfer.
25.6.12
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP1 module is disabled. Control of the I
be taken when the P bit of the SSP1STAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCL1IF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
DS41413B-page 272
Note: T
SLEEP OPERATION
EFFECTS OF A RESET
MULTI-MASTER MODE
SCL
SDA
Write to SSP1CON2,
Falling edge of
9th clock
BRG
= one Baud Rate Generator period.
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
2
set PEN
C slave module can receive
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to setup Stop condition
2
C bus may
T
SCL brought high after T
BRG
Preliminary
P
SCL = 1 for T
after SDA sampled high. P bit (SSP1STAT<4>) is set.
T
BRG
25.6.13
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCL1IF, and reset the
I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSP1BUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deas-
serted and the respective control bits in the SSP1CON2
register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSP1IF bit will be set.
A write to the SSP1BUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I
can be taken when the P bit is set in the SSP1STAT
register, or the bus is Idle and the S and P bits are
cleared.
2
C port to its Idle state
PEN bit (SSP1CON2<2>) is cleared by
hardware and the SSP1IF bit is set
BRG
BRG
, followed by SDA = 1 for T
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
(Figure
2010 Microchip Technology Inc.
BRG
25-31).
2
C bus is free,
2
C bus
2
C
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