ATTINY261A-MN Atmel, ATTINY261A-MN Datasheet - Page 32

• Manufacturer Part Number: ATTINY261A-MN
• Description: IC MCU AVR 2K FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B, 256 B, 512 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 105 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
6.5
6.5.1
6.5.2
32
Clock Output Buffer
Register Description
ATtiny261A/461A/861A
OSCCAL – Oscillator Calibration Register
CLKPR – Clock Prescale Register
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is
the previous clock period, and T2 is the period corresponding to the new prescaler setting.
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. Note that the clock will not be output during reset and the normal operation
of I/O pin will be overridden when the fuse is programmed. Any clock source, including the inter-
nal oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler
is used, it is the divided system clock that is output.
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal Oscillator to remove
process variations from the oscillator frequency. A pre-programmed calibration value is automat-
ically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
2 on page
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7:0 bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the low-
est frequency, and a setting of 0xFF gives the highest.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit
0x31 (0x51)
Read/Write
Initial Value
Bit
0x28 (0x48)
Read/Write
Initial Value
186. Calibration outside that range is not guaranteed.
Table 19-2 on page
7
CAL7
R/W
7
CLKPCE
R/W
0
6
CAL6
R/W
6
–
R
0
5
CAL5
R/W
186. The application software can write this register to change
5
–
R
0
Device Specific Calibration Value
4
CAL4
R/W
4
–
R
0
3
CAL3
R/W
3
CLKPS3
R/W
See Bit Description
2
CAL2
R/W
2
CLKPS2
R/W
1
CAL1
R/W
1
CLKPS1
R/W
0
CAL0
R/W
0
CLKPS0
R/W
8197B–AVR–01/10
Table 19-
OSCCAL
CLKPR