PIC16F688-E/ST Microchip Technology, PIC16F688-E/ST Datasheet - Page 461

• Manufacturer Part Number: PIC16F688-E/ST
• Description: IC MCU FLASH 4KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ST

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-TSSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 0.9 mm
• Length: 5 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.2
1997 Microchip Technology Inc.
Control Register
bit 7
bit 6
bit 5
bit 4
bit 3:2
bit 1:0
Register 25-1: LCDCON Register
bit 7
LCDEN: Module Drive Enable bit
1 = LCD drive enabled
0 = LCD drive disabled
SLPEN: LCD Display Sleep Enable bit
1 = LCD module will stop operating during SLEEP
0 = LCD module will continue to display during SLEEP
Unimplemented: Read as '0'
VGEN: Voltage Generator Enable bit
1 = Internal LCD Voltage Generator Enabled, (powered-up)
0 = Internal LCD Voltage Generator powered-down, voltage is expected to be
CS1:CS0: Clock Source Select bits
00 = Fosc/256
01 = T1CKI (Timer1)
1x = Internal RC oscillator
LMUX1:LMUX0: Common Selection bits
Specifies the number of commons and the bias method
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
LCDEN
R/W-0
LMUX1:LMUX0
provided externally
00
01
10
11
SLPEN
R/W-0
Static
1/2
1/3
1/4
W = Writable bit
U-0
—
MULTIPLEX
(COM0)
(COM0, 1)
(COM0, 1, 2)
(COM0, 1, 2, 3)
R/W-0
VGEN
- n = Value at POR reset
R/W-0
Section 25. LCD
CS1
Static
BIAS
1/3
1/3
1/3
R/W-0
CS0
Max # of Segments
LMUX1
R/W-0
DS31025A-page 25-3
32
31
30
29
bit 0
LMUX0
R/W-0
25