PIC16F688-E/ST Microchip Technology, PIC16F688-E/ST Datasheet - Page 83

• Manufacturer Part Number: PIC16F688-E/ST
• Description: IC MCU FLASH 4KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ST

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-TSSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 0.9 mm
• Length: 5 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.1.4
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit of the
EECON1 register, and then set control bit RD of the
EECON1 register. Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle to read the data. This causes the sec-
ond
EECON1,RD
available in the very next cycle, in the EEDAT and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions.
EXAMPLE 9-3:
© 2009 Microchip Technology Inc.
;
;
instruction
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
BSF
BSF
NOP
NOP
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
”
READING THE FLASH PROGRAM
MEMORY
instruction to be ignored. The data is
immediately following the “
EEADR
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADR
EECON1
EECON1, EEPGD
EECON1, RD
EEDAT
EEDAT, W
LOWPMBYTE
EEDATH, W
HIGHPMBYTE
STATUS, RP1
FLASH PROGRAM READ
;
;
;MS Byte of Program Address to read
;
;LS Byte of Program Address to read
;
;Point to PROGRAM memory
;EE Read
;First instruction after BSF EECON1,RD executes normally
;Any instructions here are ignored as program
;memory is read in second cycle after BSF EECON1,RD
;
;W = LS Byte of Program Memory
;
;W = MS Byte of Program EEDAT
;
;Bank 0
BSF
EEDAT and EEDATH registers will hold this value until
another read or until it is written to by the user (during
a write operation).
Note 1: The two instructions following a program
2: If the WR bit is set when EEPGD = 1, it
memory read are required to be NOP’s.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
will be immediately reset to ‘0’ and no
operation will take place.
instruction
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