ATTINY24V-10MUR Atmel, ATTINY24V-10MUR Datasheet - Page 119
![MCU AVR 2KB FLASH 10MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY24V-10MUR
Manufacturer Part Number
ATTINY24V-10MUR
Description
MCU AVR 2KB FLASH 10MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24V-10MUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.3.2
8006K–AVR–10/10
SPI Master Operation Example
Figure 14-3. Three-wire Mode, Timing Diagram
The three-wire mode timing is shown in
erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI
is sampled at positive edges, and DO is changed (USI Data Register is shifted by one) at nega-
tive edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0
are used. In other words, data is sampled at negative and output is changed at positive edges.
The USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram
The following code demonstrates how to use the USI module as a SPI Master:
CYCLE
1. The slave and master devices set up their data outputs and, depending on the protocol
2. The master software generates a clock pulse by toggling the USCK line twice (C and
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
USCK
USCK
SPITransfer:
DO
DI
used, enable their output drivers (mark A and B). The output is set up by writing the
data to be transmitted to the USI Data Register. The output is enabled by setting the
corresponding bit in the Data Direction Register of Port A. Note that there is not a pre-
ferred order of points A and B in the figure, but both must be at least one half USCK
cycle before point C, where the data is sampled. This is in order to ensure that the data
setup requirement is satisfied. The 4-bit counter is reset to zero.
D). The bit values on the data input (DI) pins are sampled by the USI on the first edge
(C), and the data output is changed on the opposite edge (D). The 4-bit counter will
count both edges.
the transfer has been completed. If USI Buffer Registers are not used the data bytes
that have been transferred must now be processed before a new transfer can be initi-
ated. The overflow interrupt will wake up the processor if it is set to Idle mode.
Depending on the protocol used the slave device can now set its output to high
impedance.
out
ldi
out
ldi
( Reference )
A
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r17,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
B
MSB
MSB
C
1
D
2
6
6
(Figure
3
5
5
14-3), a bus transfer involves the following steps:
Figure 14-3
4
4
4
At the top of the figure is a USCK cycle ref-
5
3
3
6
2
2
ATtiny24/44/84
7
1
1
LSB
LSB
8
E
119
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