ATTINY2313A-SUR Atmel, ATTINY2313A-SUR Datasheet - Page 155
ATTINY2313A-SUR
Manufacturer Part Number
ATTINY2313A-SUR
Description
MCU AVR 2KB FLASH 20MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY2313A-MU.pdf
(270 pages)
Specifications of ATTINY2313A-SUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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16. USI – Universal Serial Interface
16.1
16.2
8246A–AVR–11/09
Features
Overview
•
•
•
•
•
•
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
refer to
listed in the
Figure 16-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly
accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register
(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register
must be read as quickly as possible to ensure that no data is lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depend-
ing on the mode configuration, see
latch between the output of the USI Data Register and the output pin, which delays the change
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Pinout ATtiny2313A/4313” on page
“Register Description” on page
USIDR
USIBR
USISR
USICR
2
4-bit Counter
“Analog Comparator” on page
3
2
1
0
3
2
1
0
D Q
LE
162.
2. Device-specific I/O Register and bit locations are
[1]
TIM0 COMP
Figure 16-1
0
1
Two-wire Clock
Control Unit
For actual placement of I/O pins
167). There is a transparent
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
155
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