PIC12F1822-I/P Microchip Technology, PIC12F1822-I/P Datasheet - Page 4

• Manufacturer Part Number: PIC12F1822-I/P
• Description: IC MCU 8BIT FLASH 8PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Embedded Interface Type: AUSART, EUSART, I2C, SPI
• No. Of Pins: 8
• No. Of Adc Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12(L)F1822/PIC16(L)F1823
EXAMPLE 1:
For other combinations of F
instruction cycle delay counts, refer to
TABLE 3:
DS80502B-page 4
BSF
BCF
MOVF
Note:
32 MHz
16 MHz
8 MHz
In
required to complete the full conversion. Each T
cycle consists of 8 T
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
Affected Silicon Revisions
F
OSC
A6
X
Figure
ADCON0, GO/DONE; Start ADC conversion
ADCON0, GO/DONE; Terminate the
ADRESH, W
The exact delay time will depend on the
choice of F
(ADCS) selection. The T
in the timing diagram above apply to this
example only. Refer to
required
configurations.
A8
1, 88 instruction cycles (T
INSTRUCTION CYCLE DELAY
COUNTS FOR OTHER F
AND T
F
F
F
F
F
F
F
OSC
OSC
OSC
OSC
OSC
OSC
OSC
T
CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
AD
/64
/32
/64
/32
/16
/32
/16
delay
AD
OSC
CY
; Provide 86
; Read conversion
COMBINATIONS
Instruction Cycle Delay
instruction cycle
delay here
conversion manually
result
periods. A fixed delay is
and the T
OSC
counts
, T
CY
Counts
Table 3
AD
Table
172
172
counts shown
86
86
43
86
43
for
AD
values and
CY
3.
OSC
) will be
for the
divisor
other
AD
3. Module: APFCON
3.1 Timer1 Gate
4. Module: Enhanced Capture Compare
4.1 Enhanced PWM
4.2 Enhanced PWM
The APFCON register is normally used to remap
the T1 Gate to an alternate pin. The T1GSEL bit of
the APFCON register is found to be not writable
and therefore the T1Gate pin cannot be
remapped. The default value for the T1GSEL bit is
0 and, therefore, the T1Gate will be found on RA4.
This affects the PIC16(L)F1823 devices only.
Work around
None.
Affected Silicon Revisions
When the PWM is configured for Full-Bridge mode
and the duty cycle is set to 0%, writing the
PxM<1:0> bits to change the direction has no
effect on PxA and PxC outputs.
Work around
Increase the duty cycle to a value greater than 0%
before changing directions.
Affected Silicon Revisions
In PWM mode, when the duty cycle is set to 0%
and the STRxSYNC bit is set, writing the STRxA,
STRxB, STRxC and the STRxD bits to enable/
disable steering to port pins has no effect on the
outputs.
Work around
Increase the duty cycle to a value greater than 0%
before enabling/disabling steering to port pins.
Affected Silicon Revisions
A6
A6
A6
X
X
X
A8
A8
A8
PWM (ECCP)
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