PIC16F1827-E/P Microchip Technology, PIC16F1827-E/P Datasheet - Page 283
![MCU PIC 8BIT 4K FLASH 18-DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F1827-E/P
Manufacturer Part Number
PIC16F1827-E/P
Description
MCU PIC 8BIT 4K FLASH 18-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1827-E/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, EUSART (SCI), SPI, USB
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
4 x 8 bit, 1 x 16 bit
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 283 of 406
- Download datasheet (4Mb)
REGISTER 24-2:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
R/C/HS-0/0
WCOL
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I
SSPxADD value of 0 is not supported. Use SSPxM = 0000 instead.
WCOL: Write Collision Detect bit
Master mode:
1 =
0 =
Slave mode:
1 =
0 =
SSPxOV: Receive Overflow Indicator bit
In SPI mode:
1 =
0 =
In I
1 =
0 =
SSPxEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 =
0 =
In I
1 =
0 =
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCLx release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
SSPxM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Reserved
1010 = SPI Master mode, clock = F
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
R/C/HS-0/0
2
2
2
2
SSPxOV
C mode:
C mode:
C Slave mode:
C Master mode:
A write to the SSPxBUF register was attempted while the I
No collision
The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
No collision
A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
No overflow
A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode
(must be cleared in software).
No overflow
Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
SSPxCON1: SSPx CONTROL REGISTER 1
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C firmware controlled Master mode (Slave idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
SSPxEN
R/W-0/0
OSC
OSC
OSC
OSC
OSC
/4
/16
/64
/(4 * (SSPxADD+1))
/ (4 * (SSPxADD+1))
(1)
R/W-0/0
CKP
Preliminary
2
C™ mode.
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
R/W-0/0
(5)
(4)
2
C™ conditions were not valid for a transmission to be started
PIC16F/LF1826/27
R/W-0/0
SSPxM<3:0>
C = User cleared
R/W-0/0
(3)
(2)
DS41391C-page 283
R/W-0/0
bit 0
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