PIC16F688T-E/SL Microchip Technology, PIC16F688T-E/SL Datasheet
PIC16F688T-E/SL
Specifications of PIC16F688T-E/SL
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PIC16F688T-E/SL Summary of contents
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... Microchip Technology Inc. PIC16F688 Data Sheet 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41203E ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Input Only Pin • Programmable Code Protection • High-Endurance Flash/EEPROM Cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years © 2009 Microchip Technology Inc. PIC16F688 Low-Power Features: • Standby Current 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 220 μ ...
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... Basic IOC Y ICSPDAT IOC Y V /ICSPCLK REF Y — (1) IOC Y MCLR/V PP IOC Y OSC2/CLKOUT IOC Y OSC1/CLKIN — — — — — — — — — — — — — — — — — — — — — — © 2009 Microchip Technology Inc. ...
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... AN7 RC4 5 — C2OUT RC5 4 — — 16 — — 13 — — 14 — — 15 — Note 1: Pull-up activated only with external MCLR configuration. © 2009 Microchip Technology Inc PIC16F688 Timers EUSART Interrupt — — IOC — — IOC T0CKI — IOC/INT — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41203E-page 4 © 2009 Microchip Technology Inc. ...
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... Internal Oscillator Block T1G T1CKI Timer0 Timer1 T0CKI Analog-to-Digital Converter V AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 REF © 2009 Microchip Technology Inc. INT 13 Data Bus Program Counter RAM 8-Level Stack 256 bytes (13 bit) File Registers RAM Addr 9 Addr MUX ...
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... CMOS Port C I/O ST CMOS USART asynchronous input ST CMOS USART asynchronous data Power — Ground reference SS Power — Positive supply DD CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description OC = Open collector output © 2009 Microchip Technology Inc. ...
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... Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory Wraps to 0000h-07FFh © 2009 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into multiple banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP0 and RP1 are bank select bits ...
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... TRISC 187h 188h 189h PCLATH 18Ah INTCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1EFh accesses 1F0h Bank 0 1FFh Bank 3 © 2009 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatched exists. © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... IOCA1 IOCA0 35, 118 --00 0000 EEDATH1 EEDATH0 78, 118 --00 0000 78, 118 VR1 VR0 63, 118 0-0- 0000 EEDAT1 EEDAT0 78, 118 0000 0000 EEADR1 EEADR0 78, 118 0000 0000 WR RD 79, 118 x--- x000 77, 118 ---- ---- 72, 118 xxxx xxxx — — 71, 118 -000 ---- © 2009 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatched exists. © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2009 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... See Section 5.1.3 “Software Programmable Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC WDT Rate 128 256 1 : 128 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IOCA register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2009 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... Disables the Timer1 overflow interrupt DS41203E-page 16 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 C2IE C1IE OSFIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TXIE TMR1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software The TMR1 register did not overflow © 2009 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE bit of the INTCON register ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> the Configuration Word register for this bit to control the BOR. DS41203E-page 18 R/W-1 U-0 U-0 (1) SBOREN — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-x POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). © 2009 Microchip Technology Inc. 2.3.2 STACK The PIC16F688 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable ...
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... CONTINUE 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR ;inc pointer ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 File Select Register Location Select 1FFh © 2009 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2009 Microchip Technology Inc. The oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. DS41203E-page 22 R/W-0 R-1 R-0 (1) IRCF0 OSTS HTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R/W-0 LTS SCS bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Upon restarting the external clock, the device will resume operation time had elapsed. © 2009 Microchip Technology Inc. PIC16F688 3.4 External Clock Modes 3 ...
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... DD ® ® and PIC ® Oscillator Design” ® Oscillator CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode © 2009 Microchip Technology Inc. ...
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... The user also needs to take into account variation due to tolerance of external RC components used. © 2009 Microchip Technology Inc. 3.5 Internal Clock Modes The oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
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... Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2009 Microchip Technology Inc. PIC16F688 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING ...
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... IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC = 0 IRCF <2:0> System Clock DS41203E-page 28 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled ≠ 0 Running Running Running © 2009 Microchip Technology Inc. ...
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... Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2009 Microchip Technology Inc. PIC16F688 When the oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)” ...
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... FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC T T OST OSC1 1022 1023 0 1 OSC2 Program Counter System Clock DS41203E-page © 2009 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2009 Microchip Technology Inc. 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
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... Detected Test Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 — — RAIF 0000 000x 0000 000x SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 © 2009 Microchip Technology Inc. ...
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... TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. ...
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... Q2 cycle), then the RAIF interrupt flag may not get set. R/W-1 R/W-1 R/W-1 ANS4 ANS3 ANS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . R/W-1 R/W-1 ANS1 ANS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IOCA<5:0>: Interrupt-on-change PORTA Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. © 2009 Microchip Technology Inc. R/W-1 U-0 R/W-1 WPUA4 — WPUA2 U = Unimplemented bit, read as ‘ ...
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... B’10001000’ ;Enable interrupt MOVWF INTCON SLEEP NOP Module” ULTRA LOW-POWER WAKE-UP INITIALIZATION ; ;Set RA0 data latch ;Turn off ; comparators ; ;RA0 to digital I/O ; ;Output high to ; charge capacitor ;Select RA0 IOC ;RA0 to input ; and clear flag ;Wait for IOC ; © 2009 Microchip Technology Inc. ...
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... Change To Comparator To A/D Converter Note 1: Comparator mode and ANSEL determines analog Input mode. © 2009 Microchip Technology Inc. 4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU Figure 4-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: • a general purpose I/O • ...
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... TRISA RD PORTA IOCA Q3 RD IOCA Interrupt-on- change To Timer0 To INT To A/D Converter Note 1: Analog Input mode is based upon ANSEL. BLOCK DIAGRAM OF RA2 (1) Analog Input Mode Weak RAPU C1OUT Enable C1OUT 1 0 I/O pin (1) Analog Input Mode PORTA © 2009 Microchip Technology Inc. ...
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... IOCA Interrupt-on- change RD PORTA © 2009 Microchip Technology Inc. 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • a Timer1 gate input • ...
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... Oscillator Circuit OSC2 PORTA TRISA INTOSC RD Mode TRISA RD PORTA IOCA EN RD IOCA Interrupt-on- change RD PORTA To Timer1 or CLKGEN Note 1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. © 2009 Microchip Technology Inc. ( Weak V DD I/O pin V SS (2) Q3 ...
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... RA5 TRISA — — TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2009 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 C1INV CIS CM2 ...
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... Bit is cleared INITIALIZING PORTC ; ;Init PORTC ;Set RC<4,1:0> to ;digital I/O ; ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs R/W-0 R/W-0 R/W-0 RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PORTC To Comparators To A/D Converter Note 1: Analog Input mode is based upon Comparator mode and ANSEL. © 2009 Microchip Technology Inc. 4.3.3 RC2/AN6 Figure 4-8 shows the diagram for this pin. The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D Converter 4 ...
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... BLOCK DIAGRAM OF RC5 PIN EUSART Out Enable V DD EUSART 1 DT Out 0 I/O Pin V SS Value on Value on Bit 0 all other POR, BOR Resets ANS0 1111 1111 1111 1111 CM0 0000 0000 0000 0000 RC0 --xx 0000 --xx 0000 TRISC0 --11 1111 --11 1111 © 2009 Microchip Technology Inc. ...
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... T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2009 Microchip Technology Inc. 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements Section 14.0 “Electrical Specifications”. © 2009 Microchip Technology Inc. as shown in ...
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... TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... Clock Source F /4 OSC T1CKI pin TMR1ON To C2 Comparator Module Timer1 Clock ( TMR1L 1 (1) T1SYNC 1 Prescaler OSC 0 Internal Clock T1CKPS<1:0> TMR1CS TMR1CS Clock Source OSC T1CKI pin 1 TMR1GE T1GINV Synchronized clock input (3) Synchronize det 2 1 C2OUT 0 T1GSS © 2009 Microchip Technology Inc. ...
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... Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2009 Microchip Technology Inc. PIC16F688 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized ...
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... TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set The device will wake- overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). © 2009 Microchip Technology Inc. ...
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... Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘ ...
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... Bit 0 all other POR, BOR Resets C2SYNC ---- --10 00-- --10 RAIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 0000 uuuu uuuu © 2009 Microchip Technology Inc. ...
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... Timer1 gate (count enable) • Output synchronization to Timer1 clock input • Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2009 Microchip Technology Inc. PIC16F688 7.1 Comparator Overview A comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output ...
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... D Q Q3*RD CMCON0 EN CL Reset OSC C2SYNC D Q Timer1 (1) clock source CMCON0 D Q Q3*RD CMCON0 EN CL Reset OSC To C1OUT pin To Data Bus Set C1IF bit ). To Timer1 Gate 0 To C2OUT pin 1 To Data Bus Set C2IF bit ). © 2009 Microchip Technology Inc. ...
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... Source Impedance Analog Voltage Threshold Voltage T © 2009 Microchip Technology Inc. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. and V . The ...
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... TRIS bit set to ‘1’ to disable the digital output driver. Pins denoted as “D” should have the corresponding TRIS bit set to ‘0’ to enable the digital output driver. Note: Comparator interrupts should be disabled during a Comparator mode change to prevent unintended interrupts. DS41203E-page 56 © 2009 Microchip Technology Inc. ...
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... C1IN C2IN C2IN+ Legend Analog Input, ports always reads ‘0’ I/O = Normal port I/O Note 1: Reads as ‘0’, unless CxINV = 1. © 2009 Microchip Technology Inc. Two Independent Comparators CM<2:0> = 100 A C1IN- (1) Off A C1IN+ A C2IN- (1) Off A C2IN+ One Independent Comparator CM<2:0> = 101 ...
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... Table 7-1. TABLE 7-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions CxINV V - > < > < Note: CxOUT refers to both the register bit and output pin. DS41203E-page 58 CxOUT © 2009 Microchip Technology Inc. ...
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... See the Comparator and Voltage Reference specifications in Section 14.0 “Electrical Specifications” for more details. © 2009 Microchip Technology Inc. PIC16F688 7.5 Comparator Interrupt Operation The comparator interrupt flag is set whenever there is a change in the output value of the comparator ...
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... A device Reset forces the CMCON0 and CMCON1 registers to their Reset states. This forces the comparator module the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the comparator disabled to consume the smallest current possible. © 2009 Microchip Technology Inc. ...
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... Four inputs multiplexed to two comparators 011 = Two common reference comparators 100 = Two independent comparators 101 = One independent comparator 110 = Two common reference comparators with outputs 111 = Comparators off. CxIN pins are configured as digital I/O © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 C1INV CIS CM2 U = Unimplemented bit, read as ‘ ...
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... Figure 7-3) and the Timer1 Block Diagram (Figure 6-1) for more information. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) © 2009 Microchip Technology Inc. R/W-1 R/W-0 T1GSS C2SYNC bit Bit is unknown ...
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... REF 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ Value Selection bits (0 ≤ VR<3:0> ≤ 15) bit 3-0 VR<3:0>: CV REF When VRR = 1: CV REF When VRR = 0: CV REF © 2009 Microchip Technology Inc. EQUATION 7- (low range REF V 0 (high range REF The full range of V the construction of the module ...
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... CM0 0000 0000 0000 0000 ---- --10 ---- --10 RAIF 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000 RA0 --x0 x000 --x0 x000 RC0 --xx 0000 --xx 0000 TRISA0 --11 1111 --11 1111 --11 1111 --11 1111 VR0 0-0- 0000 0-0- 0000 © 2009 Microchip Technology Inc. ...
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... Sleep. Figure 8-1 shows the block diagram of the ADC. FIGURE 8-1: ADC BLOCK DIAGRAM RA0/AN0 RA1/AN1/V REF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 © 2009 Microchip Technology Inc. (ADC) allows V DD VCFG = 0 V REF VCFG = 1 000 001 A/D 010 ...
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... Section 14.0 “Electrical Specifications” for more information. Table 8-1 gives examples of appropriate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC adversely affect the ADC result. periods AD specification AD , any changes in the RC clock frequency, which may © 2009 Microchip Technology Inc. ...
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... FIGURE 8-2: ANALOG-TO-DIGITAL CONVERSION Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit © 2009 Microchip Technology Inc DEVICE OPERATING FREQUENCIES (VDD > 3.0V Device Frequency (F 20 MHz 8 MHz (2) (2) 100 ns 250 ns (2) (2) 200 ns 500 ns (2) 1.0 μs ...
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... The ADFM bit of the ADCON0 register controls the output format. Figure 8-4 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 © 2009 Microchip Technology Inc. ...
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... SLEEP instruction causes the present conver- RC sion to be aborted and the ADC module is turned off, although the ADON bit remains set. © 2009 Microchip Technology Inc. PIC16F688 8.2.5 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital Conversion: 1 ...
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... ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space DS41203E-page 70 © 2009 Microchip Technology Inc. ...
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... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 U-0 ADCS0 — ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x ADRES3 ADRES2 bit Bit is unknown R/W-x R/W-x — — bit Bit is unknown R/W-x R/W-x ADRES9 ADRES8 bit Bit is unknown R/W-x R/W-x ADRES1 ADRES0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2009 Microchip Technology Inc. can be started. To calculate the minimum acquisition time, Equation 8-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC) ...
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... REF DS41203E-page Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale REF Transition HOLD REF Sampling Switch (kΩ) © 2009 Microchip Technology Inc. ...
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... RC5 TRISA — — TRISA5 TRISC — — TRISC5 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. © 2009 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — — ...
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... PIC16F688 NOTES: DS41203E-page 76 © 2009 Microchip Technology Inc. ...
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... EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory. © 2009 Microchip Technology Inc. PIC16F688 9.1 EEADR and EEADRH Registers The EEADR and EEADRH registers can address maximum of 256 bytes of data EEPROM maximum of 4K words of program EEPROM ...
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... Bit is cleared R/W-0 R/W-0 EEDAT1 EEDAT0 bit Bit is unknown R/W-0 R/W-0 EEADR1 EEADR0 bit Bit is unknown (1) or Read from program memory R/W-0 R/W-0 EEDATH1 EEDATH0 bit Bit is unknown R/W-0 R/W-0 EEADRH1 EEADRH0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read © 2009 Microchip Technology Inc. U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘ ...
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... Memory Address to write ; ;Data Memory Value to write ; ;Point to DATA memory ;Enable writes ;Disable INTs. ;SEE AN576 ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Enable INTs. ;Wait for interrupt to signal write complete ;Disable writes © 2009 Microchip Technology Inc. ...
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... EEDATH, W MOVWF HIGHPMBYTE BCF STATUS, RP1 © 2009 Microchip Technology Inc. EEDAT and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). Note 1: The two instructions following a program memory read are required to be NOP’s. ...
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... POR, BOR Resets RD x--- x000 0--- q000 ---- ---- ---- ---- EEADR0 0000 0000 0000 0000 EEADRH0 ---- 0000 ---- 0000 EEDAT0 0000 0000 0000 0000 EEDATH0 --00 0000 --00 0000 RABIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 © 2009 Microchip Technology Inc. ...
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... SPBRGH SPBRG BRGH BRG16 © 2009 Microchip Technology Inc. The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
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... Register 10-2 and Register 10-3, respectively. DS41203E-page 84 MSb Data Stop Recovery F OSC ÷ x16 x64 0 0 FERR 0 Register 10-1, CREN OERR RCIDL RSR Register LSb • • • ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2009 Microchip Technology Inc. ...
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... If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. © 2009 Microchip Technology Inc. Note 1: When the SPEN bit is set, the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the EUSART receiver is enabled ...
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... TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. © 2009 Microchip Technology Inc. ...
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... TRISC5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2009 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE RAIE ...
Page 90
... PEIE peripheral interrupt enable bit of the INT- CON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. Receiving Data Receive Interrupts © 2009 Microchip Technology Inc. ...
Page 91
... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2009 Microchip Technology Inc. PIC16F688 10.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...
Page 92
... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Start bit Stop bit 7/8 bit © 2009 Microchip Technology Inc. ...
Page 93
... TRISC5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2009 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE RAIE ...
Page 94
... Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
Page 96
... Auto-Baud Detect mode is enabled (clears when auto-baud is complete Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41203E-page 94 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 97
... TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. © 2009 Microchip Technology Inc. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...
Page 98
... F = 8.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — — — — — — — — 2404 0.16 207 — 71 9615 0. 10417 0. 19231 0. 55556 -3. — — — © 2009 Microchip Technology Inc. ...
Page 99
... Microchip Technology Inc. SYNC = 0, BRGH = 1, BRG16 = 3.6864 MHz F = 2.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...
Page 100
... F = 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) 1666 300.1 0.04 832 416 1202 0.16 207 207 2404 0.16 103 51 9615 0. 10417 0. 19.23k 0. — — — — — — — © 2009 Microchip Technology Inc. ...
Page 101
... SPBRGH Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. © 2009 Microchip Technology Inc. and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. ...
Page 102
... RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL. Cleared due to User Read of RCREG © 2009 Microchip Technology Inc. Auto Cleared ...
Page 103
... After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. © 2009 Microchip Technology Inc Q1Q2 Q3 Q4 Cleared due to User Read of RCREG Sleep Ends 10 ...
Page 104
... BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here SENDB (send Break control bit) DS41203E-page 102 bit 0 bit 1 bit 11 Break Auto Cleared © 2009 Microchip Technology Inc. Stop bit ...
Page 105
... A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCTL register. Setting the SCKP bit sets © 2009 Microchip Technology Inc. PIC16F688 the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. ...
Page 106
... TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 TRISC0 --11 1111 --11 1111 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2009 Microchip Technology Inc. ...
Page 107
... Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2009 Microchip Technology Inc. PIC16F688 10.4.1.8 Synchronous Master Reception Set- up: 1 ...
Page 108
... TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 TRISC0 --11 1111 --11 1111 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2009 Microchip Technology Inc. ...
Page 109
... TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2009 Microchip Technology Inc. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...
Page 110
... TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 TRISC0 --11 1111 --11 1111 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2009 Microchip Technology Inc. ...
Page 111
... Sleep • Code Protection • ID Locations • In-Circuit Serial Programming™ © 2009 Microchip Technology Inc. The PIC16F688 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the ...
Page 112
... Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory (2000h-3FFFh), which can be accessed only during programming. “PIC12F6XX/16F6XX Memory Program- ming Specification” (DS41204) for more information. DS41203E-page 110 space See © 2009 Microchip Technology Inc. ...
Page 113
... The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. © 2009 Microchip Technology Inc. Reserved FCMEN (4) PWRTE ...
Page 114
... A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 11-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 14.0 “Electrical Specifications” for pulse width specifications Enable PWRT Enable OST © 2009 Microchip Technology Inc. Chip_Reset Q ...
Page 115
... An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull- © 2009 Microchip Technology Inc. FIGURE 11- This kΩ ...
Page 116
... Brown-out Reset and the Power-up Timer will be re-initialized. Once V rises above V , the Power-up Timer will execute a BOD 64 ms Reset. ( & slew rate. A Reset is DD falls below V for less DD BOD rises DD while the Power-up Timer BOD V BOD V BOD © 2009 Microchip Technology Inc. ...
Page 117
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 11-1) for operation of all register bits. © 2009 Microchip Technology Inc. 11.2.6 POWER CONTROL (PCON) REGISTER The Power Control (PCON) register (address 8Eh) has two Status bits to indicate what type of Reset that last occurred ...
Page 118
... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS41203E-page 116 T PWRT T OST T PWRT T OST ) DD T PWRT T OST © 2009 Microchip Technology Inc. ...
Page 119
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 11-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit © 2009 Microchip Technology Inc. MCLR Reset Power-on WDT Reset Reset (1) ...
Page 120
... uuu1 0uuu -uuu uuuu ---u uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu ---- uuuu u-u- uuuu uuuu uuuu uuuu uuuu u--- uuuu ---- ---- uuuu uuuu -uuu ---- PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu © 2009 Microchip Technology Inc. ...
Page 121
... The GIE is cleared to disable any further interrupt. • The return address is pushed onto the stack. • The PC is loaded with 0004h. © 2009 Microchip Technology Inc. PIC16F688 For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles ...
Page 122
... If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set. Wake-up (If in Sleep mode) T0IF T0IE INTF INTE RAIF RAIE PEIE GIE © 2009 Microchip Technology Inc. Interrupt to CPU ...
Page 123
... INTCON GIE PEIE T0IE PIE1 EEIE ADIE RCIE PIR1 EEIF ADIF RCIF Legend unknown unchanged, — = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. © 2009 Microchip Technology Inc (1) (2) Interrupt Latency Inst ( — ...
Page 124
... STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS41203E-page 122 However, if © 2009 Microchip Technology Inc. ...
Page 125
... Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP © 2009 Microchip Technology Inc. A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTRC 65536, giving the WDT a nominal range 268s ...
Page 126
... WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 T0SE PSA PS2 PS1 PWRTE WDTE FOSC2 FOSC1 R/W-0 R/W-0 WDTPS0 SWDTEN bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets ---0 1000 PS0 1111 1111 1111 1111 FOSC0 — — © 2009 Microchip Technology Inc. ...
Page 127
... External Interrupt from INT pin. 7. EUSART Receive Interrupt. 8. ULPWU Interrupt. © 2009 Microchip Technology Inc. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction ( prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 128
... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. DS41203E-page 126 OST (2) T (3) Interrupt Latency Processor in Sleep Inst( Inst( Dummy Cycle not been 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) © 2009 Microchip Technology Inc. ...
Page 129
... To Normal Connections * Isolation devices (as required) © 2009 Microchip Technology Inc. 11.10 In-Circuit Debugger Since in-circuit debugging requires access to the data and MCLR pins, MPLAB 14-pin device is not practical. A special 20-pin PIC16F688 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user ...
Page 130
... PIC16F688 NOTES: DS41203E-page 128 © 2009 Microchip Technology Inc. ...
Page 131
... PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. © 2009 Microchip Technology Inc. PIC16F688 TABLE 12-1: OPCODE FIELD DESCRIPTIONS ...
Page 132
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2009 Microchip Technology Inc. ...
Page 133
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. BCF Syntax: k Operands: Operation: Status Affected: ...
Page 134
... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. ...
Page 135
... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2009 Microchip Technology Inc. PIC16F688 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 ≤ ...
Page 136
... Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2009 Microchip Technology Inc. ...
Page 137
... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2009 Microchip Technology Inc. PIC16F688 RETLW Return with literal in W Syntax: [ label ] RETLW k 0 ≤ k ≤ 255 Operands: k → (W); Operation: TOS → PC Status Affected: None ...
Page 138
... Subtract W from literal [ label ] SUBLW k 0 ≤ k ≤ 255 k - (W) → (W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. W > ≤ W<3:0> > k<3:0> W<3:0> ≤ k<3:0> © 2009 Microchip Technology Inc. ...
Page 139
... The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. © 2009 Microchip Technology Inc. PIC16F688 XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k 0 ≤ ...
Page 140
... PIC16F688 NOTES: DS41203E-page 138 © 2009 Microchip Technology Inc. ...
Page 141
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. PIC16F688 13.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 142
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2009 Microchip Technology Inc. ...
Page 143
... Microchip Technology Inc. 13.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 144
... K L security ICs, CAN ® IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2009 Microchip Technology Inc. ® ...
Page 145
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. ........................................................................... -0. )...............................................................................................................± ...
Page 146
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 14-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 2.0 2.5 DS41203E-page 144 8 10 Frequency (MHz) ± 5% ± 2% ± 1% 3.0 3.5 4.0 4 AND TEMPERATURE DD 5.0 5.5 © 2009 Microchip Technology Inc. ...
Page 147
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which V DD © 2009 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40°C ≤ T Min Typ† Max Units 2.0 — ...
Page 148
... MHz OSC XT Oscillator mode MHz OSC XT Oscillator mode MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode kHz OSC LFINTOSC mode MHz OSC HFINTOSC mode MHz OSC HFINTOSC mode MHz OSC (3) EXTRC mode MHz OSC HS Oscillator mode © 2009 Microchip Technology Inc. ...
Page 149
... Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2009 Microchip Technology Inc. -40°C ≤ T ≤ +85°C for industrial A Min Typ† ...
Page 150
... Conditions Note WDT, BOR, Comparators, V and REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , both comparators enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2009 Microchip Technology Inc. ...
Page 151
... Higher leakage current may be measured at different input voltages. 4: See Section 9.0 “Data EEPROM and Flash Program Memory Control” for additional information. 5: Including OSC2 in CLKOUT mode. © 2009 Microchip Technology Inc. PIC16F688 -I (Industrial) PIC16F688 -E (Extended) Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 152
... Minimum operating MIN voltage ms Year Provided no other specifications are violated E/W -40°C ≤ T ≤ +85°C A E/W -40°C ≤ T ≤ +85°C A E/W +85°C ≤ T ≤ +125° Minimum operating MIN voltage V ms Year Provided no other specifications are violated © 2009 Microchip Technology Inc. ...
Page 153
... Ambient Temperature Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (P © 2009 Microchip Technology Inc. Typ Units 69.8 C/W 14-pin PDIP package 85.0 C/W 14-pin SOIC package 100 ...
Page 154
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 14-3: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output DS41203E-page 152 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance L © 2009 Microchip Technology Inc. ...
Page 155
... All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. © 2009 Microchip Technology Inc ...
Page 156
... A 2.0V ≤ V ≤ 5.5V, MHz DD -40°C ≤ T ≤ +85°C (Ind.), A -40°C ≤ T ≤ +125°C (Ext kHz μ 2.0V, -40°C to +85°C DD μ 3.0V, -40°C to +85°C DD μ 5.0V, -40°C to +85°C DD © 2009 Microchip Technology Inc. ...
Page 157
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2009 Microchip Technology Inc. Fetch Read Q1 Q2 OS11 OS20 ...
Page 158
... Asserted low. FIGURE 14-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41203E-page 156 BOR 37 33 HYST (Device not in Brown-out Reset) © 2009 Microchip Technology Inc. ...
Page 159
... By design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 μF and 0.01 μF values in parallel are recommended. © 2009 Microchip Technology Inc. ≤ +125°C Min Typ† Max Units 2 — — ...
Page 160
... T — OSC 49 Max Units Conditions — ns — ns — ns — ns — prescale value (2, 4, ..., 256) — ns — ns — ns — ns — ns — ns — prescale value ( — ns — kHz 7 T — Timers in Sync OSC mode © 2009 Microchip Technology Inc. ...
Page 161
... Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section 7.10 “Comparator Voltage Reference” for more information. © 2009 Microchip Technology Inc. ≤ +125°C Min Typ† ± 5.0 — ...
Page 162
... V pin, whichever is selected as reference input. REF DD Conditions = 5.12V REF V = 5.12V REF = 5.12V REF = 5.12V REF Absolute minimum to ensure 1 LSb accuracy During V acquisition. AIN Based on differential HOLD AIN During A/D conversion cycle. © 2009 Microchip Technology Inc. ...
Page 163
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following T 2: See Section 8.3 “A/D Acquisition Requirements” for minimum conditions. © 2009 Microchip Technology Inc. ≤ +125°C Min Typ† Max Units μs 1.6 — ...
Page 164
... SLEEP instruction to be executed. DS41203E-page 162 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the CY ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the NEW_DATA DONE NEW_DATA DONE © 2009 Microchip Technology Inc. ...
Page 165
... Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz © 2009 Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC PIC16F688 DD 5.5V 5 ...
Page 166
... Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Temp) + 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 MHz © 2009 Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD EC Mode 6 MHz 8 MHz 10 MHz 12 MHz F OSC vs. F OVER V ...
Page 167
... Typical: Statistical Mean @25×C Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + Maximum: Mean (Worst-case Temp) + 3σ 1000 800 600 400 200 0 2 2.5 © 2009 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs ...
Page 168
... Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + Maximum: Mean (Worst-case Temp) + 3σ 1,000 3 (-40°C to 125°C) ( 40×C t 125×C) 800 600 400 200 0 2 2.5 © 2009 Microchip Technology Inc. vs. V OVER F (XT MODE) DD OSC 4 MHz 1 MHz ...
Page 169
... FIGURE 15-9: I vs. V OVER Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125° 2.0 2.5 © 2009 Microchip Technology Inc. vs. V (EXTRC MODE MHz 1 MHz 3 3 (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ Maximum Typical 3.0 3.5 4.0 ...
Page 170
... Typical: Statistical Mean @25°C 1,600 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,400 1,200 1,000 800 600 400 200 0 125 kHz 250 kHz © 2009 Microchip Technology Inc. 32 kHz Maximum 32 kHz Typical 3 3 (V) DD vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC ...
Page 171
... Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 © 2009 Microchip Technology Inc. vs. F OVER V (HFINTOSC MODE) OSC DD 500 kHz 1 MHz 2 MHz V (V) DD vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) ...
Page 172
... Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 140 (-40°C to 125°C) 120 100 2.0 2.5 © 2009 Microchip Technology Inc. vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Maximum (Sleep Mode all Peripherals Disabled) Max. 125°C Max. 85°C 3.0 3.5 4 ...
Page 173
... FIGURE 15-17: TYPICAL WDT I 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0V 2.5V © 2009 Microchip Technology Inc. OVER TEMPERATURE DD Maximum Typical 3.5 4.0 4.5 V (V) DD vs. V (25° 3.0V 3.5V 4.0V V (V) DD PIC16F688 5 ...
Page 174
... WDT PERIOD vs Typical: Statistical Mean @25°C Maximum: Mean + 3σ (-40°C to 125°C) Maximum: Mean + 3σ 2.0 2.5 © 2009 Microchip Technology Inc. vs. V OVER TEMPERATURE PD DD Max. 125°C Max. 85°C 3.0V 3.5V 4.0V V (V) DD OVER TEMPERATURE DD Max. (125°C) Max. (85°C) ...
Page 175
... REF PD 140 Typical: Statistical Mean @25°C Maximum: Mean + 3σ (-40°C to 125°C) 120 100 2.0 2.5 © 2009 Microchip Technology Inc. Vdd = 5V Maximum Typical Minimum 25°C 85°C Temperature (°C) OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85°C Typical 3 ...
Page 176
... Typical: Statistical Mean @25°C 0.7 Maximum: Mean + 3σ 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5.0 5.5 6.0 © 2009 Microchip Technology Inc. OVER TEMPERATURE (LOW RANGE) DD Max. 125°C Max. 85°C Typical 3.0 3.5 4 3.0V) DD (VDD = 3V, -40×C TO 125×C) Typical 25° ...
Page 177
... Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 1.0 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 © 2009 Microchip Technology Inc. = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 ...
Page 178
... FIGURE 15-27: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1.3 1.1 0.9 0.7 0.5 2.0 2.5 © 2009 Microchip Technology Inc. = 5.0V -1.5 -2.0 -2.5 -3.0 -3.5 I (mA) OH vs. V OVER TEMPERATURE ...
Page 179
... Maximum: Mean + 3 (-40×C to 125×C) (-40°C to 125°C) 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 2.0 2.5 © 2009 Microchip Technology Inc. vs (ST Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (32 kHz) DD Max. 125°C Max. 85°C Typ. 25° ...
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... FIGURE 15-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 700 1.5V)/2 600 Note input = V CM 500 V- input = Transition from V 400 300 200 100 0 2.0 © 2009 Microchip Technology Inc. + 100 2.5 4 100 2.5 4.0 V (V) DD PIC16F688 Max. 125° ...
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... Microchip Technology Inc. OVER TEMPERATURE (31 kHz) DD LFINTOSC 31Khz Max. -40°C Typ. 25°C Min. 85°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 3 ...
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... FIGURE 15-35: MAXIMUM HFINTOSC START-UP TIMES vs 85°C 25°C 10 -40° 2.0 2.5 3.0 © 2009 Microchip Technology Inc. OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25° ...
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... FIGURE 15-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2009 Microchip Technology Inc. OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD PIC16F688 4 ...
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... TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 FIGURE 15-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2009 Microchip Technology Inc. 3.0 3.5 4.0 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD PIC16F688 (85°C) DD 4.5 5.0 5.5 (125°C) DD 5.0 5.5 DS41203E-page 182 ...
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... FIGURE 15-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2009 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD PIC16F688 (-40°C) DD 5.0 5.5 DS41203E-page 183 ...
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... NOTES: © 2009 Microchip Technology Inc. PIC16F688 DS41203E-page 184 ...
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... Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2009 Microchip Technology Inc. PIC16F688 Example ...
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... PIC16F688 16.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± 1RWH N NOTE 1RWHV DS41203E-page 186 PLO %RG\ >3', © 2009 Microchip Technology Inc. ...
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... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2009 Microchip Technology Inc ...
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... PIC16F688 1RWH DS41203E-page 188 © 2009 Microchip Technology Inc. ...
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... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2009 Microchip Technology Inc ...
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... PIC16F688 For the most current package drawings, please see the Microchip Packaging Specification located at Note: http://www.microchip.com/packaging DS41203E-page 190 © 2009 Microchip Technology Inc. ...
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... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2009 Microchip Technology Inc. EXPOSED PAD E2 2 ...
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... PIC16F688 1RWH DS41203E-page 192 © 2009 Microchip Technology Inc. ...
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... Updated Peripheral Features, page 1; Deleted Note 1, page 13; Updated the Typical Info. in Param. OS18, Table 14-3; Added sub-section 10.3.2 (Auto-Baud Overflow, page 100) to Chapter 10; Added SOIC, TSSOP, QFN Package Land Patterns. © 2009 Microchip Technology Inc. PIC16F688 APPENDIX B: MIGRATING FROM OTHER PIC ...
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... PIC16F688 NOTES: DS41203E-page 194 © 2009 Microchip Technology Inc. ...
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... Interrupt Logic ........................................................... 120 MCLR Circuit............................................................. 113 On-Chip Reset Circuit ............................................... 112 PIC16F688.................................................................... 5 RA1 Pins ..................................................................... 38 RA2 Pin....................................................................... 38 RA3 Pin....................................................................... 39 RA4 Pin....................................................................... 39 © 2009 Microchip Technology Inc. PIC16F688 RA5 Pin ...................................................................... 40 RC0 and RC1 Pins ..................................................... 43 RC2 and RC3 Pins ..................................................... 43 RC4 Pin ...................................................................... 44 RC5 Pin ...................................................................... 44 Resonator Operation .................................................. 24 Timer1 ...
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... RRF .......................................................................... 136 SLEEP ...................................................................... 136 SUBLW ..................................................................... 136 SUBWF..................................................................... 137 SWAPF ..................................................................... 137 XORLW .................................................................... 137 XORWF .................................................................... 137 Summary Table ........................................................ 130 INTCON Register................................................................ 15 Internal Oscillator Block INTOSC Specifications ........................................... 154, 155 Internal Sampling Switch (R ) Impedance........................ 73 SS Internet Address ............................................................... 199 Interrupts........................................................................... 119 © 2009 Microchip Technology Inc. ...
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... PICSTART Plus Development Programmer ..................... 142 PIE1 Register ...................................................................... 16 Pin Diagram ...................................................................... 2, 3 Pinout Description PIC16F688.................................................................... 6 PIR1 Register...................................................................... 17 PORTA................................................................................ 33 Additional Pin Functions ............................................. 34 © 2009 Microchip Technology Inc. PIC16F688 ANSEL Register ................................................. 34 Interrupt-on-Change ........................................... 34 Ultra Low-Power Wake-up............................ 34, 36 Weak Pull-up ...................................................... 34 Associated registers ................................................... 41 Pin Descriptions and Diagrams .................................. 37 RA0............................................................................. 37 RA1 ...
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... REF EE W Wake-up on Break ............................................................ 100 Wake-up Using Interrupts ................................................. 125 Watchdog Timer (WDT).................................................... 123 Associated Registers ................................................ 124 Clock Source ............................................................ 123 Modes ....................................................................... 123 Period ....................................................................... 123 Specifications ........................................................... 157 WDTCON Register ....................................................... 9, 124 WPUA Register................................................................... 35 WWW Address ................................................................. 199 WWW, On-Line Support ....................................................... 4 © 2009 Microchip Technology Inc. ...