PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 409
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PIC16F688-I/STG
Manufacturer Part Number
PIC16F688-I/STG
Description
IC PIC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
Specifications of PIC16F688-I/STG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- Current page: 409 of 688
- Download datasheet (3Mb)
1997 Microchip Technology Inc.
Legend C
VA
Rs
V
I
R
SS
C
LEAKAGE
PIN
T
IC
HOLD
Section 22. Basic 8-bit A/D Converter
RAx
Figure 22-3:
C
5 pF
PIN
Note 1: The reference voltage (V
Note 2: The charge holding capacitor (C
Note 3: The maximum recommended impedance for analog sources is 10 k . This is
Note 4: After a conversion has completed, a 2.0 T
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
VARIOUS JUNCTIONS
out.
required to meet the pin leakage specification.
can begin again. During this time the holding capacitor is not connected to the
selected A/D input channel.
Analog Input Model
V
DD
V
V
T
T
= 0.6V
= 0.6V
REF
I leakage
500 nA
) has no effect on the equation, since it cancels itself
R
IC
HOLD
1k
) is not discharged after each conversion.
V
SS
DD
AD
Sampling
Switch
delay must complete before acquisition
6V
5V
4V
3V
2V
R
SS
Sampling Switch
5 6 7 8 9 10 11
V
SS
C
( k )
HOLD
= 51.2 pF
DS31022A-page 22-7
22
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