ATTINY24A-MUR Atmel, ATTINY24A-MUR Datasheet - Page 149
ATTINY24A-MUR
Manufacturer Part Number
ATTINY24A-MUR
Description
MCU AVR 2KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.13.5
8183C–AVR–03/11
DIDR0 – Digital Input Disable Register 0
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
See
• Bit 5 – Res: Reserved Bit
This is a reserved bit in ATtiny24A/44A/84A. For compatibility with future devices always write
this bit to zero.
• Bit 4 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see
page
• Bit 3 – Res: Reserved Bit
This bit is reserved bit in the ATtiny24A/44A/84A and will always read as what was wrote there.
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 16-7.
• Bits 7:0 – ADC7D:ADC0D: ADC[7:0] Digital Input Disable
When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled.
The corresponding PIN register bit will always read as zero when this bit is set. When an analog
signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
Bit
0x01 (0x21)
Read/Write
Initial Value
“ADCSRB – ADC Control and Status Register B” on page
148.
ADTS2
0
0
0
0
1
1
1
1
ADC Auto Trigger Source Selections
ADC7D
R/W
7
0
ADC6D
ADTS1
R/W
6
0
0
0
1
1
0
0
1
1
ADC5D
R/W
5
0
ADC4D
R/W
ADTS0
4
0
0
1
0
1
0
1
0
1
“ADCL and ADCH – ADC Data Register” on
ADC3D
R/W
3
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ATtiny24A/44A/84A
ADC2D
R/W
2
0
130.
ADC1D
R/W
1
0
ADC0D
R/W
0
0
.
DIDR0
149
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