ATTINY25V-10MUR Atmel, ATTINY25V-10MUR Datasheet - Page 119
![MCU AVR 2KB FLASH 10MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY25V-10MUR
Manufacturer Part Number
ATTINY25V-10MUR
Description
MCU AVR 2KB FLASH 10MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-20MU.pdf
(236 pages)
Specifications of ATTINY25V-10MUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.5.3
2586M–AVR–07/10
USISR – USI Status Register
The Status Register contains interrupt flags, line status flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has
been detected. When three-wire mode or output disable mode has been selected any edge on
the SCK pin will set the flag.
If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener-
ated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit.
Clearing this bit will release the start detection hold of USCL in two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). If the
USIOIE bit in USICR and the Global Interrupt Enable Flag are set an interrupt will also be gener-
ated when the flag is set. The flag will only be cleared if a one is written to the USIOIF bit.
Clearing this bit will release the counter overflow hold of SCL in two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When two-wire mode is selected, the USIPF Flag is set (one) when a stop condition has been
detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag.
This signal is useful when implementing two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The
flag is only valid when two-wire mode is used. This signal is useful when implementing Two-wire
bus master arbitration.
• Bits 3:0 – USICNT[3:0]: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or
written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge
detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe
bits. The clock source depends on the setting of the USICS[1:0] bits.
For external clock operation a special feature is added that allows the clock to be generated by
writing to the USITC strobe bit. This feature is enabled by choosing an external clock source
(USICS1 = 1) and writing a one to the USICLK bit.
Note that even when no wire mode is selected (USIWM[1:0] = 0) the external clock input
(USCK/SCL) can still be used by the counter.
Bit
0x0E
Read/Write
Initial Value
USISIF
R/W
7
0
USIOIF
R/W
6
0
USIPF
R/W
5
0
USIDC
R
4
0
USICNT3
R/W
3
0
USICNT2
R/W
2
0
USICNT1
R/W
1
0
USICNT0
R/W
0
0
USISR
119
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