ATTINY13A-SN Atmel, ATTINY13A-SN Datasheet - Page 47
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ATTINY13A-SN
Manufacturer Part Number
ATTINY13A-SN
Description
IC MCU AVR 1KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SN
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-SN
Manufacturer:
MICROCHIP
Quantity:
3 000
9.3
9.3.1
9.3.2
8126E–AVR–07/10
Register Description
MCUCR – MCU Control Register
GIMSK – General Interrupt Mask Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Table 9-2.
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT[5:0] pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt
Vector. PCINT[5:0] pins are enabled individually by the PCMSK Register.
Bit
0x35
Read/Write
Initial Value
Bit
0x3B
Read/Write
Initial Value
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00
R
7
–
0
R
7
–
0
0
1
0
1
Table 9-2 on page
PUD
R/W
INT0
R/W
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
6
0
6
0
R/W
PCIE
R/W
SE
5
0
5
0
SM1
R/W
4
0
R
47. The value on the INT0 pin is sampled before
4
–
0
SM0
R/W
3
0
R
3
–
0
R
2
–
0
R
2
–
0
ISC01
R/W
1
0
R
1
–
0
ISC00
R/W
0
0
R
0
–
0
MCUCR
GIMSK
47