ATTINY25V-10SH Atmel, ATTINY25V-10SH Datasheet - Page 42
![IC MCU AVR 2KB FLASH 10MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY25V-10SH
Manufacturer Part Number
ATTINY25V-10SH
Description
IC MCU AVR 2KB FLASH 10MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-20MU.pdf
(236 pages)
Specifications of ATTINY25V-10SH
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.2.1
8.2.2
42
ATtiny25/45/85
Power-on Reset
External Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
V
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
Figure 8-2.
Figure 8-3.
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer
than the minimum pulse width (see
ate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a
reset. When the applied signal reaches the Reset Threshold Voltage – V
edge, the delay counter starts the MCU after the Time-out period – t
CC
is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as
INTERNAL
INTERNAL
TIME-OUT
TIME-OUT
CC
RESET
RESET
RESET
RESET
V
V
decreases below the detection level.
CC
CC
“System and Reset Characteristics” on page
MCU Start-up, RESET Tied to V
MCU Start-up, RESET Extended Externally
V
V
V
POT
POT
RST
CC
t
TOUT
rise. The RESET signal is activated again, without any delay,
“System and Reset Characteristics” on page
CC
V
RST
t
TOUT
170. The POR is activated whenever
TOUT
– has expired.
RST
– on its positive
170) will gener-
2586M–AVR–07/10
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