ATTINY20-XUR Atmel, ATTINY20-XUR Datasheet - Page 120

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ATTINY20-XUR

Manufacturer Part Number
ATTINY20-XUR
Description
MCU AVR 2KB FLASH 12MHZ 14TSSOP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY20-XUR

Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
15.9
15.10 ADC Accuracy Definitions
120
Noise Canceling Techniques
ATtiny20
In order to avoid distortion from unpredictable signal convolution, signal components higher than
the Nyquist frequency (f
quency components with a low-pass filter before applying the signals as inputs to the ADC.
Figure 15-8. Analog Input Circuitry
Note:
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. When conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in
is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as
described in
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior, as follows:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to V
The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and
any stray or parasitic capacitance inside the device. The value given is worst case.
ADCn
Section 15.7 on page
Section 15.12 on page
ADC
/2) should not be present. The user is advised to remove high fre-
I
IH
119. This is especially the case when system clock frequency
I
IL
123. A good system design with properly placed, external
CC
and GND pins as possible.
1..100 kohm
C
S/H
= 14 pF
n
-1.
V
CC
REF
/2
8235B–AVR–04/11
in 2
n
steps

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