ATTINY4-TS8R Atmel, ATTINY4-TS8R Datasheet - Page 59

• Manufacturer Part Number: ATTINY4-TS8R
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4-TS8R

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

11.5.1
11.5.2
11.5.3
8127D–AVR–02/10
Input Capture Trigger Source
Noise Canceler
Using the Input Capture Unit
tion mode (WGM03:0) bits must be set before the TOP value can be written to the ICR0
Register. When writing the ICR0 Register the high byte must be written to the ICR0H I/O location
before the low byte is written to ICR0L.
For more information on how to access the 16-bit registers refer to
on page
The main trigger source for the Input Capture unit is the Input Capture pin (ICP0).
Timer/Counter0 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog
Comparator Input Capture (ACIC) bit in “ACSR – Analog Comparator Control and Status Regis-
ter”. Be aware that changing trigger source can trigger a capture. The Input Capture Flag must
therefore be cleared after the change.
Both the Input Capture pin (ICP0) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the T0 pin
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-
form Generation mode that uses ICR0 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP0 pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC0) bit in
Timer/Counter Control Register B (TCCR0B). When enabled the noise canceler introduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICR0 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR0 Register before the next event occurs, the ICR0 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR0 Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR0
Register has been read. After a change of the edge, the Input Capture Flag (ICF0) must be
72.
(Figure 11-3 on page
56). The edge detector is also
“Accessing 16-bit Registers”
ATtiny4/5/9/10
59