PIC10F204-I/P Microchip Technology, PIC10F204-I/P Datasheet - Page 56
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PIC10F204-I/P
Manufacturer Part Number
PIC10F204-I/P
Description
IC PIC MCU FLASH 256X12 8DIP
Manufacturer
Microchip Technology
Series
PIC® 10Fr
Datasheets
1.PIC10F200T-IOT.pdf
(96 pages)
2.PIC10F200T-IOT.pdf
(6 pages)
3.PIC10F200T-IOT.pdf
(18 pages)
4.PIC10F202-EP.pdf
(88 pages)
Specifications of PIC10F204-I/P
Program Memory Type
FLASH
Program Memory Size
384B (256 x 12)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
3
Ram Size
16 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC10F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
16 B
Interface Type
USB
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC103003 - BOARD DEMO PIC10F CAP TOUCHAC162059 - HEADER INTRFC MPLAB ICD2 8/14PINAC164037 - MODULE SKT 6L PROMATE II SOT23
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC10F204-I/P
Manufacturer:
MICROCHIP
Quantity:
336
Part Number:
PIC10F204-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC10F200/202/204/206
BTFSS
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
DS41239A-page 54
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0
0
skip if (f<b>) = 1
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a 2-cycle instruction.
Subroutine Call
[ label ] CALL k
0
(PC) + 1
k
(Status<6:5>)
0
Subroutine call. First, return
address (PC + 1) is pushed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
Status<6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
Clear f
[ label ] CLRF
0
00h
1
The contents of register ‘f’ are
cleared and the Z bit is set.
f
b < 7
k
f
PC<7:0>;
PC<8>
Z
31
31
255
(f);
Top-of-Stack;
PC<10:9>;
f
Preliminary
CLRW
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected: TO, PD
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
Clear W
[ label ] CLRW
None
00h
1
The W register is cleared. Zero bit
(Z) is set.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h
0
1
1
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
Complement f
[ label ] COMF
0
d
(f)
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
f
[0,1]
Z
WDT prescaler (if assigned);
TO;
PD
(dest)
2004 Microchip Technology Inc.
31
(W);
WDT;
f,d