M3087BFLAGP#U3 Renesas Electronics America, M3087BFLAGP#U3 Datasheet - Page 310
![IC M32C/87B MCU FLASH 144LQFP](/photos/12/31/123137/m3087bflagp_u3_sml.jpg)
M3087BFLAGP#U3
Manufacturer Part Number
M3087BFLAGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFLAGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFLAGP#U3M3087BFLAGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 286 of 587
17.2.2
Table 17.24
NOTES:
Data format
Baud rate
Transmit/receive control
Transmit start condition
Receive start condition
Interrupt request generation
timing
Error detection
Selectable function
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, the content of the UiRB register is undefined. The U5RR bit in the IIO0IR register
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.24 lists specifications of
UART mode. Table 17.25 lists pin settings. Figure 17.51 shows register settings. Figure 17.52 shows an
example of a transmit operation. Figure 17.53 shows an example of a receive operation.
and the U6RR bit in the IIO9IR register remain unchanged as 0 (interrupt not requested).
Clock Asynchronous (UART) Mode
Item
UART Mode Specifications
• Data length: selectable among 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selectable among odd, even, or none
• Stop bit: selectable from 1 bit or 2 bits long
fj / (16 (m + 1))
Selectable among CTS function, RTS function or CTS/RTS function disabled
To start transmit operation, all of the following must be met:
To start receive operation, all of the following must be met:
Transmit interrupt (The UiIRS bit in the U56CON register selects one of the following):
Receive interrupt:
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first or MSB first
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Apply a low-level (“L”) signal to the CTSi pin when the CTS function is selected
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• The RI bit is 1 (no data in UiRB register) when RTS function is used.
• The start bit is detected
• The UiIRS bit is set to 0 (no data in the UiTB register):
• The UiIRS bit is set to 1 (transmit operation completed):
• When data is transferred from the UARTi receive shift register to the UiRB register
Overrun error occurs when the preceding bit of the final stop bit of the next data (the
first stop bit when selecting 2 stop bits) is received before reading the UiRB register
Framing error occurs when the number of the stop bits set by the STPS bit in the
UiMR register is not detected
Parity error occurs when parity is enabled and the received data does not have the
correct even or odd parity set by the PRY bit in the UiMR register.
Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs
Data is transmitted or received from either bit 0 or bit 7
fj = f1, f8, f2n
m: setting value of the UiBRG register (00h to FFh) (i = 5, 6)
fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is
When the above two conditions are met, the RTSi pin output an “L” signal.
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
when the final stop bit is output from the UARTi transmit shift register
(receive operation completed)
set to 1 (external clock)
(2)
(1)
, fEXT
Specification
17. Serial Interfaces (UART5 and UART6)
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