M30627FJPGP#U9C Renesas Electronics America, M30627FJPGP#U9C Datasheet - Page 392
![IC M16C/62P MCU FLASH 128LQFP](/photos/12/30/123024/m30627fjpgp_u9c_sml.jpg)
M30627FJPGP#U9C
Manufacturer Part Number
M30627FJPGP#U9C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U9CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
24.11 A/D Converter
Figure 24.4
Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger
occurs).
When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref connected),
start A/D conversion after passing 1 µs or longer.
To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors
between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN0_i, AN2_i) each and the AVSS pin.
Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 24.4 is an example connection of each
pin.
Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the ADTRG
pin is set to “0” (input mode).
When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
The φAD frequency must be 12MHz or less. Without sample-and-hold function, limit the φAD frequency to
250kHz or more. With the sample and hold function, limit the φAD frequency to 1MHz or more.
When changing an A/D operating mode, select analog input pin again in the CH2 to CH0 bits in the ADCON0
register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Jan 10, 2006
Use of Capacitors to Reduce Noise
NOTES :
ANi: ANi, AN0_i and AN2_i (i=0 to 7)
VCC2
VCC1
1. C1 ≥ 0.47 µ F, C2 ≥ 0.47 µ F, C3 ≥ 100pF, C4 ≥ 0.1 µ F, C5 ≥ 0.1 µ F (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Page 375 of 390
C4
C5
Microcomputer
VCC1
VSS
VCC2
VSS
AVCC
VREF
AVSS
ANi
C1
C2
VCC1
C3
24. Precautions
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