M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet
M30245FCGP#U1
Specifications of M30245FCGP#U1
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M30245FCGP#U1 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M30245 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M30245 Group The M30245 group is a 16-bit microcomputer based on the M16C family core technology that uses a high performance silicon gate CMOS process with an M16C/62 Series CPU core. It comes packaged ...
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M30245 Group Table of Contents Features ................................................................................................................................................. 1 Description ............................................................................................................................................ 3 Memory ................................................................................................................................................ 12 Central Processing Unit ..................................................................................................................... 13 Reset .................................................................................................................................................... 16 Special Function Registers ................................................................................................................ 18 Processor Modes ................................................................................................................................ 26 System Clock ....................................................................................................................................... 38 Power Control ..................................................................................................................................... 45 Frequency ...
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M30245 Group Applications USB peripherals, such as telephones, audio systems, office equipment, communications equipment, portable devices, scanners, digital cameras, and memory card readers. Block Diagram Figure 1 block diagram of the M30245 group Port P0 Port ...
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M30245 Group Performance outline Table 1 performance outline of the M30245 group. Table 1.1. M30245 Group performance outline Parameters Number of basic Instructions Shortest Instruction execution time ROM Memory size RAM P0 to P8, P10 (excl P8 Input/Output ...
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M30245 Group Pin Configuration Figure 1.2 shows the pin configuration (top view). Table 1.2 lists the pin cross references and Table 1.3 describes the pin functions /AND_OE /AND_WE 1 ...
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M30245 Group Table 1.2. Pin cross reference Pin Control Port Interrupt No UVcc BYTE 7 CNVss CIN COUT 6 10 RESET 11 X OUT 12 ...
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M30245 Group Table 1.2 Pin cross reference Pin Control Port Interrupt No Vcc 61 P3 ...
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M30245 Group Pin description Table 1.3 Port Function Pin Name Power supply input Vcc Vss CPU mode switch CNVss External data bus width select BYTE input Reset input RESET Clock input X IN Clock output X OUT Analog power supply ...
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M30245 Group Pin description Table 1.3 Port Function P6 I/O port P6 0 UART/SSI CTS/RTS/SS/WS CLK/SCK RxD/SCL/STxD/RX TxD/SDA/SRxD/XMT port P7 0 Timer OUT UART CTS/RTS/SS/WS CLK/SCK RxD/SCL/STxD TxD/SDA/SRxD LED drive LED P8 P8 ...
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M30245 Group Renesas plans to release the following products in the M30245 group: (1) Support for Flash memory version and mask ROM versions (2) ROM capacity: 128 or 64 Kbytes (3) Package: 100P6Q-A Plastic molded LQFP Figure 1.3 shows the ...
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M30245 Group USB Overview The M30245 group is a single-chip PC peripheral microcontroller that is compliant with the Universal Serial Bus (USB) Version 2.0 specification for full-speed USB operation (12Mbps). This device provides an interface between a USB- equipped host ...
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M30245 Group Functional Block Operation The M30245 group contains many functional blocks in a single chip. These blocks include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are ...
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M30245 Group Central Processing Unit The CPU has a total of 13 registers shown in Figure 1.6. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 ...
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M30245 Group Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of ...
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M30245 Group • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0"; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when ...
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M30245 Group Reset There are two kinds of resets: software and hardware. In both cases, operation is the same after the reset. Software Reset Writing a "1" to bit 3 of the processor mode register 0 (address 0004 microcomputer. A ...
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M30245 Group X IN More than 20 cycles are needed Microprocessor mode BYTE = “H” RESET BCLK Address RD WR CS0 Microprocessor mode BYTE = “L” Address RD WR CS0 Single chip mode Address Figure 1.9. Reset sequence ____________ Table ...
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M30245 Group Special Function Registers Tables 1.6 to 1.13 show the peripheral control registers, their addresses, names, acronyms, and values after reset. Table 1.6. SFR Map (1) Register name Address 0000 16 0001 16 0002 16 0003 16 0004 Processor ...
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M30245 Group Table 1.7. SFR Map (2) Address 0040 16 0041 Key input interrupt control register 16 0042 UART2 receive/ACK interrupt control register 16 0043 UART1/3 Bus collision interrupt control register 16 0044 INT1 interrupt control register 16 0045 Timer ...
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M30245 Group Table 1.8. SFR Map (3) Address 0280 16 USB address register 0281 16 0282 16 USB power management register 0283 16 0284 16 USB interrupt status register 0285 16 0286 16 USB interrupt clear register 0287 16 0288 ...
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M30245 Group Table 1.9. SFR Map (4) Address 02C0 16 USB EP2 OUT max packet size register 02C1 16 02C2 16 USB EP2 OUT write count register 02C3 16 02C4 16 USB EP2 OUT FIFO configuration register 02C5 16 02C6 ...
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M30245 Group Table 1.10. SFR Map (5) Address 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030A 16 030B 16 030C 16 030D 16 030E 16 030F 16 ...
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M30245 Group Table 1.11. SFR Map (6) Address 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034A 16 034B 16 034C 16 034D 16 034E 16 034F 16 ...
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M30245 Group Table 1.12. SFR Map (7) Register name Address 0380 Count start flag 16 0381 Clock prescaler reset flag 16 0382 One-shot start flag 16 0383 Trigger select register 16 0384 Up-down flag 16 0385 16 0386 16 Timer ...
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M30245 Group Table 1.13. SFR Map (8) Register name Address 03C0 16 AD register 0 03C1 16 03C2 16 AD register 1 03C3 16 03C4 16 AD register 2 03C5 16 03C6 16 AD register 3 03C7 16 03C8 16 ...
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M30245 Group Processor Modes One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. Figure ...
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M30245 Group Processor mode register 0 (Note Note 1: Set bit 1 of the protect register (address 000A Note 2: For hardware reset Note 3: Valid in ...
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M30245 Group Single-chip mode Memory expansion mode 00000 16 SFR area 00400 16 Internal RAM area XXXXX 16 04000 16 Inhibited D0000 16 YYYYY 16 Internal ROM area FFFFF 16 Figure 1.11. Memory map of each processor mode Memory expansion ...
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M30245 Group Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space bits (1M bytes address space). When bit ...
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M30245 Group Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. ...
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M30245 Group Table 1.16. External areas specified by the chip select signals Process or mode CS0 30000 to CFFFF Memory 16 expansion mode (640 Kbytes) 30000 to FFFFF Microprocessor 16 mode (832 Kbytes) Read/write signals With a 16-bit data bus ...
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M30245 Group The ALE signal The ALE signal can be used by an external device to latch the address from the address bus. This signal indicates when the address on the bus is valid. Latch the address when the ALE ...
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M30245 Group HOLD signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to the ___________ HOLD pin places the microcomputer in the hold state at the end of the ...
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M30245 Group Software wait A software wait of one to three BCLK cycles can be inserted by setting bits the chip select control register (address 0008 16 Software waits can be set independently for each of ...
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M30245 Group No Wait Read signal Write signal PM16=0 Data bus PM16=0 Write signal PM16=1 Data bus PM16=1 Address bus Chip select With 1 Wait Read signal Write signal PM16=0 Data bus PM16=0 Write signal PM16=1 Data bus PM16=1 Address ...
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M30245 Group With 2 Waits BCLK Read signal Write signal PM16=0 Data bus PM16=0 Write signal PM16=1 Data bus PM16=1 Address bus Chip select With 3 Waits BCLK Read signal Write signal PM16=0 Data bus PM16=0 Write signal PM16=1 Data ...
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M30245 Group Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.17 shows the protect register. The values in the processor mode ...
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M30245 Group System Clock Clock-generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Figure 1.18 shows the block diagram of the clock-generating circuit. Table 1.23 lists ...
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M30245 Group Figure 1.19 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.20 shows some examples of subclock circuits, one ...
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M30245 Group Clock Control Main clock The main clock is generated by the main clock oscillation circuit. After a reset, this clock is divided produce the BCLK. The clock can be stopped using the main clock stop ...
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M30245 Group System clock control registers Figure 1.21 shows the system clock control registers 0 and 1. System clock control register 0 (Note System clock control register 1 (Note ...
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M30245 Group Stop Mode Writing "1" to the all-clock stop control bit (bit 0 at address 0007 stop mode. In stop mode, the content of the internal RAM is retained provided that Vcc remains above 2V. Because the oscillation of ...
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M30245 Group Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock ...
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M30245 Group Table 1.26. System clock control registers 0 and 1 operating mode settings CM17 CM16 CM07 Invalid Invalid Invalid Invalid 1 Invalid Invalid 1 • Divide ...
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M30245 Group Power control The following is a description of the three available power control modes. Figure 1.22 shows the state transition diagram for these modes. Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the ...
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M30245 Group State Transitions for Stop and Wait modes All oscillators stopped Interrupt Stop Mode CM10 = "1" All oscillators stopped CM10 = "1" Stop Mode All oscillators stopped Interrupt Stop Mode CM10 = "1" State Transitions for normal mode ...
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M30245 Group Frequency synthesizer circuit The frequency synthesizer circuit generates a 48MHz clock (f are a multiple of the external input reference clock f(X f(Xin) Prescaler FSP 03DE Figure 1.23. Frequency Synthesizer Circuit The frequency synthesizer consists of a prescaler, ...
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M30245 Group Frequency Synthesizer Control register Figure 1.24. Frequency Synthesizer Control register (FSC) Frequency Synthesizer Clock Control register Figure 1.25. Frequency Synthesizer Clock Control register ...
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M30245 Group Multiplier Clock multiplied up version of clock f VCO the clock (f ) input to the multiplier from the prescaler is as follows: PIN • 2(n+1) where n is the decimal ...
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M30245 Group Interrupts Figure 1.29 lists the types of interrupts. • Maskable: An interrupt that can be enabled or disabled by the interrupt enable flag (I flag) or can have its interrupt priority changed by the priority level. • Non-maskable: ...
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M30245 Group Hardware Interrupts Hardware interrupts are classified into two types - special interrupts and peripheral I/O interrupts. Special interrupts Special interrupts are non-maskable interrupts. • Reset Reset occurs if an "L" is input to the RESET pin. ______ • ...
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M30245 Group Interrupt Routine Interrupt vector tables 1If an interrupt request is accepted, program execution branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.30 ...
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M30245 Group Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Before enabling interrupts, the user must load the INTB register with the address of the first entry in the table. ...
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M30245 Group Interrupt control The interrupt request bit is set by hardware to "0" when an interrupt request is received. The interrupt request bit can also be set by software to "0". (Do not set to "1".) INT0, INT1, and ...
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M30245 Group Table 1.29. Addresses in interrupt control register Interrupt control register Key input UART2 receive / ACK UART1 / UART3 Bus collision INT1 Timer A1 USB EP0 Timer A2 UART1 receive / ACK / Serial Sound Interface 1 receive ...
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M30245 Group Example 1:Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I The number of NOP instruction is as follows. PM20=1(1 wait) : ...
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M30245 Group Interrupt Response Time 'interrupt response time' is the period between when an interrupt occurs and when the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to ...
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M30245 Group 1 2 BCLK Internal Address 0000 Address bus Interrupt Internal information Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. ...
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M30245 Group Table 1.31 shows the settings of interrupt priority levels and Table 1.32 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: •interrupt enable flag (I ...
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M30245 Group Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority. Figure 1.35 shows the circuit that judges the interrupt priority. UART1 receive/ACK/SSI1 receive UART0 transmit/NACK/SSI0 transmit UART1 transmit/NACK/SSI1 ...
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M30245 Group Flag changes When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack ...
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M30245 Group INT interrupt _______ _______ INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit in the interrupt control register (0044 register (035F ). 16 For an external ...
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M30245 Group Pull-up transistor KIE3 Port P10 P10 / Pull-up Port P10 transistor P10 / KIE2 Pull-up transistor Port P10 P10 / Pull-up Port P10 transistor P10 / KIE0 Pull-up Port P10 ...
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M30245 Group Occurrence timing of the key-input interrupt With the Key-input interrupt enabled, Port 10 pins that are enabled in the Key-input mode register are set to input mode and become Key-input interrupt pins (KI a Key-input interrupt pin. At ...
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M30245 Group Address-Match Interrupt An address-match interrupt is generated when the address-match interrupt address register contents match the program counter value. Two address-match interrupts can be set, each of which can be enabled and disabled by an address-match interrupt enable ...
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M30245 Group _______ The NMI interrupt _______ The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc with a pull-up resistor if unused. Do not go into _______ stop mode when the NMI pin set ...
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M30245 Group Clearing the Interrupt request bit Even when the IR bit (bit 3 of the interrupt control register) is cleared to "0" (interrupt not requested), it may not actually get cleared to "0" depending on the instruction used to ...
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M30245 Group Watchdog Timer The watchdog timer can detect a runaway program 15-bit counter that decrements using the clock derived from dividing the BCLK by the prescaler. A watchdog timer interrupt is generated when an underflow occurs ...
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M30245 Group BCLK HOLD Write to the watchdog timer start register (address 000E ) 16 RESET Figure 1.42. Block diagram of Watchdog timer Watchdog timer control register Watchdog timer start register ...
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M30245 Group Universal Serial Bus Features • USB Specification Revision 2.0 compliant • Support of full-speed operation (12 Mbps) • Support of all USB transfer types: ........................ Isochronous ................................................................. Bulk ................................................................. Control ................................................................. Interrupt • Built-in 3.25 Kbyte FIFO as ...
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M30245 Group The USB Function Interrupt has multiple interrupt sources that can be enabled within the USB Function Interrupt Enable Register (USBIE). EP0 Interrupt The EP0 interrupt is generated when one of the following events occur: • A data set ...
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M30245 Group USB Suspend Interrupt A USB Suspend Interrupt is generated when the USB FCU does not detect any bus activity on D+/D- (in J-state) for at least 3ms. The USB Suspend Interrupt Control register (SUSPIC) contains the USB Suspend ...
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M30245 Group EP0 OUT FIFO with control write continuous transfer mode enabled The USB FCU updates the OUT_BUF_RDY flag to "1" after: • It has successfully received a data set equal to 128 bytes or a short packet from the ...
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M30245 Group CASE 1: The host sends three 8-byte packets and one 2-byte packet. When the core receives the last 2-byte packet, the OUT_BUF_RDY flag is set (because of a short packet) indicating the CPU can unload the data. At ...
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M30245 Group Double Buffer Mode: The CPU writes a "1" to the SET_IN_BUF_RDY bit of the corresponding EPx IN CSR after the CPU finishes writing a data set up to its buffer size to the buffer (updates the IN_BUF_STS1 & ...
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M30245 Group Double Buffer Mode: After the CPU writes a data set equal to its buffer size to the buffer, the USB FCU updates the IN_BUF_STS1 & IN_BUF_STS0 flags. • If the buffer is immediately available to accept another data ...
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M30245 Group EP1-4 OUT (Receive) FIFOs The CPU reads data from the endpoint’s FIFO Data Register. The read pointer automatically increments word accessing mode byte accessing mode after a read. The CPU must ...
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M30245 Group The CPU writes a "1" to the CLR_OUT_BUF_RDY bit after a data set has been unloaded from the buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags). • If the buffer has one more data set in ...
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M30245 Group OUT Endpoint FIFO Flush A software flush causes the USB FCU to act data set has been unloaded from the buffer. The user must only set the flush bit when OUT_BUF_STS1 = 1, which indicates ...
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M30245 Group USB Special Function Registers The MCU controls USB operation through the use of special function registers. Some USB-related special function registers have a mix of read/write, read only, and write only register bits. Additionally, the bits may be ...
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M30245 Group USB Control Register The USB Control Register, shown in Figure 1.45, is used to control the USB FCU. This register is not reset by USB reset signaling. After the USB is enabled (USBC7 set to "1"), a minimum ...
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M30245 Group Power Management Register The USB Power Management Register, shown in Figure 1.47, is used for power management in the USB FCU. SUSPEND State Flag: When the USB FCU does not detect any bus activity on D+/D- (in the ...
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M30245 Group USB Interrupt Status register (b8) (b15 Figure 1.48. USB Interrupt Status register (USBIS) USB Function Interrupt Clear Register The USB Function Interrupt Clear register, shown in Figure 1.49, ...
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M30245 Group USB Function Interrupt Enable Register The USB Function Interrupt Enable register, shown in Figure 1.50 is used to enable the corresponding interrupt status conditions that can generate a USB Function interrupt. When the bit of a corresponding interrupt ...
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M30245 Group USB ISO Control Register The USB ISO Control Register, shown in Figure 1.52, contains the isochronous data transfer control and status information. • ISO_UPD The ISO_UPD bit is a global bit for endpoints 1-4 and works with IN ...
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M30245 Group USB Endpoint Enable Register The USB Endpoint Enable Register, shown in Figure 1.53, is used to enable/disable an individual endpoint. EP0 is always enabled and cannot be disabled by firmware. All endpoints are disabled after reset. USB Endpoint ...
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M30245 Group USB Endpoint 0 CSR The Endpoint 0 CSR (Control & Status register), shown in Figure 1.55, contains the control and status information for EP0. • EP0CSR0 (OUT_BUF_RDY): A status flag, "1" indicates a SETUP packet or an OUT ...
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M30245 Group • EP0CSR5 (SETUP_END): A status flag, "1" indicates a premature completion of a control transfer when one of the following events occurs: • A control transfer ends before the specific length of data is transferred during the data ...
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M30245 Group USB Endpoint x OUT Control and Status register (b8) (b15 Figure 1.55. USB Endpoint 0 Control and Status register (EP0CS) USB Endpoint 0 MAXP Register The USB Endpoint 0 MAXP Register, shown in Figure ...
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M30245 Group USB Endpoint 0 WRT CNT Register The USB Endpoint 0 WRT CNT Register, shown in Figure 1.57, contains the number of bytes of the current data set in the OUT buffer. The USB FCU sets the value in ...
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M30245 Group • INxCSR6 (FLUSH): The CPU writes a "1" to this bit to flush the IN buffer. • When there is one data set in the IN buffer, a flush causes the IN buffer to be empty. • When ...
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M30245 Group USB Endpoint x IN MAXP Register ( The USB Endpoint x IN MAXP Register, shown in Figure 1.59, indicates the maximum packet size (MAXP) of EPx IN packet. The default values for all EPx ...
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M30245 Group USB Endpoint x OUT CSR ( The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.61, contains control and status information for the respective OUT EP 1-4. • OUTxCSR0 (OUT_BUF_STS0) ...
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M30245 Group • OUTxCSR11 (ISO): The CPU writes "1" to this bit to set the endpoint as an isochronous data transfer endpoint. • OUTxCSR12 (SEND_STALL): The CPU writes "1" to this bit when the endpoint is stalled (receiver halt). The ...
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M30245 Group USB Endpoint x OUT MAXP Register ( The USB Endpoint x OUT MAXP register, shown in Figure 1.62, indicates the maximum packet size (MAXP) of EPx OUT packet. The default values for all EPx ...
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M30245 Group USB Endpoint x OUT FIFO configuration Register ( The USB Endpoint x OUT FIFO Configuration Register, shown in Figure 1.64, is used to select various FIFO configura- tions. When double buffer bit is set, ...
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M30245 Group USB Endpoint x OUT FIFO Data Register ( The USB Endpoint x OUT FIFO Data Registers, shown in Figure 1.66 are the USB OUT (receive) FIFO data registers. The CPU reads data from these ...
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M30245 Group Vbus Detect The Vbus Detect function will detect when the USB host is powered-up during USB self-powered operation. Self- powered operation means the microcontroller has a power source external to the USB. This type of connection requires the ...
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M30245 Group To avoid receiving a false Vbus detect interrupt at start-up, the Vbus detect should be enabled before enabling the Vbus detect interrupt. Use the following procedure when enabling the Vbus detect function: 1) Enable Vbus detect by setting ...
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M30245 Group Direct memory access controller This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is ...
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M30245 Group Table 1.37. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred DMA request factors (Note) Channel priority Transfer unit Transfer address direction Transfer mode DMA interrupt request generation timing Active Inactive Forward address ...
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M30245 Group DMA0 request cause select register (Note DMA1 request cause select register (Note Figure 1.71. DMAC register (1) Rev.2.00 Oct 16, 2006 page ...
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M30245 Group DMA2 request cause select register (Note Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read. Note: Software is always enabled. DMA3 request cause ...
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M30245 Group DMAi control register DMAi source pointer (i=0-3) (b23) (b19 DMAi destination pointer (i=0-3) (b23) (b19 DMAi transfer counter (i=0-3) (b15) (b8 Figure 1.73. DMAC ...
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M30245 Group Transfer modes Single transfer mode DMA transfer occurs until the tranfer counter underflows. Afterward, the DMA becomes inactive. Repeat transfer mode The DMA remains active even after the transfer counter underflows. The transfer counter and forward direction address ...
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M30245 Group Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of ...
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M30245 Group Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to ...
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M30245 Group (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address CPU use bus RD WR Data CPU use bus (2) 16-bit transfers and the source address is odd Transferring 16-bit data on ...
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M30245 Group Table 1.38a. DMA transfer cycles Transfer unit Bus width 16-bit (BYTE = "L") 8-bit transfers (DMBIT = "1") 8-bit (BYTE = "H") 16-bit (BYTE = "L") 16-bit transfers (DMBIT = "0") 8-bit (BYTE = "H") Table 1.38b. Coefficient ...
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M30245 Group Timer A Except in event counter mode, Timers A0 through A4 all have the same function. Use the Timer Ai mode register ( bits 0 and 1 to choose the desired mode. Timer A ...
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M30245 Group C32 TA0 IN TA1 IN TA2 IN TA3 IN TA4 IN Figure 1.77. Timer A block diagram (2) Rev.2.00 Oct 16, 2006 page 111 of 264 REJ03B0005-0200 f ...
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M30245 Group Timer Ai register ( (Note 1) (b15 b8 Timer mode Event counter mode One-shot timer mode 16-bit PWM 8-bit PWM Note 1 : Read and write data in 16-bit units. Note ...
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M30245 Group Timer Ai mode register ( Count start flag Clock prescaler reset flag ...
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M30245 Group Up/down flag (Note One-shot start flag Figure 1.80. Timer A-related register (3) Rev.2.00 Oct 16, 2006 page 114 of 264 REJ03B0005-0200 ...
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M30245 Group Timer mode In this mode, the timer counts an internally generated count source. Timer A in timer mode specifications are shown in Table 1.39. Figure 1.81 shows the Timer Ai mode register in timer mode. Table 1.39. Timer ...
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M30245 Group Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single- phase external signal. Timers A2, A3, and A4 can count a single-phase and ...
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M30245 Group Table 1.41. Timer specifications in event counter mode (when processing two-phase pulse signal) Item •Two-phase pulse signals input to TAi Count Source • Up count or down count can be selected by two-phase pulse signal • Count operation ...
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M30245 Group Timer Ai mode register ( Figure 1.82. Timer Ai mode register in event counter mode (not using two-phase processing) Timer Ai mode register ( ...
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M30245 Group One-shot timer mode In this mode, the timer operates only once. Table 1.42 shows the timer specifications for Timer A in one-shot timer mode. When a trigger occurs, the timer starts counting down until it reaches 0000 mode ...
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M30245 Group Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. Table 1.43 shows the timer specification for Timer in pulse width modulation mode. In this mode, the counter functions as ...
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M30245 Group Timer Ai mode register ( Figure 1.85. Timer Ai mode register in pulse width modulation mode Condition : Reload register = 0003 (rising edge of TAi ...
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M30245 Group Condition : Reload register high-order 8 bits = 02 Reload register low-order 8 bits = 02 External trigger (falling edge of TAi Count source (Note1) TA pin input signal iIN Underflow signal of 8-bit prescaler (Note2) PWM pulse ...
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M30245 Group Precautions Timer mode The value of the counter can be read, with arbitrary timing, by reading the Timer Ai register while a count is in progress. Reading the Timer Ai register with the reload timing gets "FFFF After ...
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M30245 Group The Timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot ...
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M30245 Group Serial Communication Serial I/O is configured as four channels: UART0 to UART3. UART0 to UART3 have an exclusive timer to generate a transfer clock so they can operate independently of one another. Figure 1.88 shows the block diagram ...
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M30245 Group RxD polarity RxDi reversing circuit Clock source selection f 1 Internal External Clock synchronous type (when internal clock is selected) CLK polarity CLKi reversing circuit CTS/RTS selected CTSi / RTSi No reverse RxD data ...
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M30245 Group UARTi transmit buffer register ( (Note) (b8) (b15 UARTi receive buffer register ( (b8) (b15 Figure 1.89. Serial I/O-related registers (1) Rev.2.00 Oct 16, 2006 page ...
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M30245 Group UARTi bit rate generator ( (Notes Note 1: Use MOV instruction to write to this register Note 2: Write a value to this register while transmit/receive is stopped. UARTi transmit/receive mode ...
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M30245 Group UARTi transmit/receive control register 0 ( UARTi transmit/receive control register 1 ( Figure 1.91. Serial I/O-related registers (3) Rev.2.00 Oct ...
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M30245 Group UARTi special mode register ( UARTi special mode register 2 ( Figure 1.92. Serial I/O-related registers (4) ...
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M30245 Group UARTi special mode register 3 ( UARTi special mode register 4 ( Figure 1.93. Serial I/O-related registers ...
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M30245 Group Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.44 list the specifica- tions of the clock synchronous serial I/O mode. Table 1.44. Clock synchronous serial ...
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M30245 Group Table 1.45 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". ...
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M30245 Group Example of transmit timing when internal clock is selected Transfer clock "1" Transmit enable "0" Data is set in UARTi transmit buffer register bit (TE) "1" Transmit buffer empty flag (Tl) "0" "H" CTSi "L" CLKi TxDi Transmit ...
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M30245 Group Polarity select function As shown in Figure 1.95 the CLK polarity select bit (bit 6 at addresses 03AC selection of the polarity of the transfer clock. • When CLK polarity select bit = "0" CLK ...
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M30245 Group Continuous receive function If the continuous receive mode enable bit (bit 5 at address 03AD placed in continuous receive mode. In this mode, when the receive buffer is read out, the unit simultaneously goes to a receive enable ...
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M30245 Group Clock asynchronous serial I/O (UART) mode UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.46 lists the specifications of the UART mode. Table 1.46. Specifications of clock asynchronous ...
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M30245 Group Table 1.47 lists the functions of the input/output pins during UART mode. Note that the period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N-channel open ...
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M30245 Group Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock "1" Transmit enable bit (TE) "0" "1" Transmit buffer empty flag (TI) "0" "H" CTSi "L" TxDi Transmit register "1" ...
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M30245 Group Example of receive timings when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source "1" Receive enable bit "0" RxDi Transfer clock Reception triggered when transfer clock "1" is generated by falling edge ...
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M30245 Group TxD, RxD I/O polarity reverse function This function reverses the TxD pin output and RxD pin input. The level of any data input or output including the start bit, stop bits and parity bit, is reversed. Set this ...
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M30245 Group UART mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card similar device. Adding some extra settings in UART mode allows the user to effect this ...
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M30245 Group Example of transmit timing when internal clock is selected Transfer clock "1" Transmit enable "0" Data is set in UARTi transmit buffer register bit (TE) "1" Transmit buffer empty flag (Tl) "0" "H" CTSi "L" CLKi TxDi D ...
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M30245 Group Parity error signal function output With the error signal output enable bit (bit 7 of addresses 03AD level from the TxDi pin when a parity error is detected. When this occurs, the generation of a transmit complete interrupt ...
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M30245 Group Bus interface mode 2 The I C bus interface mode is provided with UARTi. When the I 0337 , and 0327 ) is set to "1", the use the I ...
Page 148
M30245 Group SDAi STSPSEL=1 Delay circuit STSPSEL=0 ACK=1 ACKD register Noise Filter Falling edge detection SCLi IICM=0 I/O port STSPSEL=0 UARTi IICM=1 Noise Filter This diagram applies to the case where the UiMR register’s SMD2 to SMD0 bits=010 IICM IICM2, ...
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M30245 Group UARTi Special Mode Register (UiSMR) 2 Bit 0 is the I C mode select bit 1. When set to "1", ports operate respectively as the SDAi data transmit/receive pin, SCLi clock input/output pin and port. A delay circuit ...
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M30245 Group UARTi Special Mode Register 2 (UiSMR2) 2 Bit 0 is the I C mode select bit 2. Table 1.50 lists the control changes by bit when the I and stop condition detection timing characteristics are shown in Figure ...
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M30245 Group When UART transmit/receive is started using this function, the content of the transmit buffer available flag does not change. Also, to use this function, select an external clock as the transfer clock. This bit is unavailable when SCLi ...
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M30245 Group UARTi Special Mode Register 4 (UiSMR4) Bit 0 is the start condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1", the start condition is generated. Bit ...
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M30245 Group Serial Interface Special Function (SPI mode) SPI mode related control bit UARTi Special Mode Register 3 (UiSMR3) Bit 0 is the SS port function enable bit. Set this bit to "1" to enable the slave select output. Bit ...
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M30245 Group Clock phase setting With bit 1 of UARTi special mode register 3 and bit 6 of UARTi transmit/receive control register 0, four combinations of transfer clock phase and polarity can be selected. Bit 6 of UARTi transmit/receive control ...
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M30245 Group "H" SS input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" (Note) High- inpedance Data input timing Note :UART2, (P7 Figure 1.112. Transmit/receive timing (CKPH=0) in slave mode ...
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M30245 Group lE Mode (UiSMR) Bit Not used in IE mode. Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is generated when RxDi and TxDi level conflict with ...
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M30245 Group (1) UiSMR register ABSCS bit (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST TxDi RxDi Input to TAj Timer Aj Timer Aj : ...
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M30245 Group Serial Sound Interface Serial Sound Interface is a synchronous serial data interface used primarily for transferring digital audio data. This functional block is compatible with the I A channel is any single output of an audio system. For ...
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M30245 Group Data transmission format The transmitter/receiver must change channels on every WS transition. If the number of SCKs within a WS high/low period exceeds the channel width (set by the user via mode bits), the transmitter continues to transmit ...
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M30245 Group The following features are supported via firmware controlled mode bits: • Simultaneous transmit and receive (through separate transmit and receive pins) synchronized to the same SCK and WS signals. • Transmit/receive data and WS synchronized to the rising ...
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M30245 Group Case I: XMTEM/RXEN goes high while WS is low SCK WS XMTEN/RXEN XMT/RX WSP = 0 XMT/RX WSP = 1 Case II: XTEN/RXEN goes high while WS is high SCK WS XMTEN/RXEN XMT/RX WSP = 0 XMT/RX WSP ...
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M30245 Group Case I : MSB - first receive data (Note) SCK MSB first data on RX line WS MSB first MSB justified Data buffer MSB first LSB justified Data buffer Case II : LSB - first receive data (Note) ...
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M30245 Group Overview The Serial Sound Interface is a serial data communication system. The parallel (MCU bus) to serial data conversion is accomplished by the shift registers. Figure 1.116 shows a description of each component of the Serial Sound Interface ...
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M30245 Group The data interface for the receiver behaves slightly different for the same case. When the receive shift register loads data into the left buffer, the state machine generates an interrupt. A word read from the MCU causes 16 ...
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M30245 Group Serial Sound Interface mode register Serial Sound Interface mode register Figure 1.122. Serial Sound Interface related registers ...
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M30245 Group Data Path The data path is designed to work with the USB on this device. Because the Serial Sound Interface is an audio interface, the USB audio class device specifications are used to define the data path. USB ...
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M30245 Group The USB FIFO is read using word accesses and each word is written to the transmit buffer. Table 1.55 lists the USB FIFO sequence operation. Note that DB refers to the MCU data bus. Table 1.55. USB FIFO ...
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M30245 Group Figure 1.123. DMA request timing in 32/24/16 bit width (transmission) Rev.2.00 Oct 16, 2006 page 166 of 264 REJ03B0005-0200 Serial Sound Interface ...
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M30245 Group Figure 1.124. DMA request timing in 32/24/16 bit width (reception) Rev.2.00 Oct 16, 2006 page 167 of 264 REJ03B0005-0200 Serial Sound Interface ...
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M30245 Group A/D converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. Pins P10 to P10 function as the analog signal input pins. Set the direction registers corresponding to a pin ...
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M30245 Group P10 Address (03C1 , 03C0 16 (03C3 , 03C2 16 (03C5 , 03C4 16 (03C7 , 03C6 16 (03C9 , 03C8 16 ...
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M30245 Group AD control register 0 (Note control register 1 (Note Figure 1.126. A/D converter-related registers (1) Rev.2.00 Oct 16, 2006 page 170 ...
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M30245 Group AD control register 2 (Note register (b8) (b15 Figure 1.127. A/D converter-related registers (2) Rev.2.00 Oct 16, 2006 ...
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M30245 Group One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conversion. Table 1.57 shows the specifications of one-shot mode. Table 1.57. One-shot mode specifications Item Function The pin ...
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M30245 Group Single sweep mode In single sweep mode, the pins selected using the A/D sweep pin select bit are used for one-by-one A/D conversion. Table 1.59 shows the specifications of single sweep mode. Table 1.59. Single sweep mode specifications ...
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M30245 Group Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A/D conversion with emphasis on the pin or pins selected using the A/ D sweep pin select bit. Table 1.61 shows the specifications of ...
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M30245 Group • Using one-shot mode or single sweep mode: Read the corresponding AD register after confirming A/D conversion is finished. (Check the A/D conversion interrupt request bit.) • Using repeat mode, repeat sweep mode 0 or repeat sweep mode ...
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M30245 Group Table 1.62. Output impedance values based on the LSB values (10-bit mode) f (Sampling IN Cycle (µs) time) (MHz) 0 cycle, 10 0.1 sample and hold bit enabled 0 cycle, Sample and ...
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M30245 Group CRC calculation circuit The Cyclic Redundancy Check (CRC) calculation circuit detects any errors in data blocks. The microcomputer uses a generator polynomial of CRC-CCITT (x The CRC code is a 16-bit code generated for a block of a ...
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M30245 Group CRC data register (b15) (b8 CRC input register b7 CRC mode register b7 CRC snoop address register (b15) (b8 Figure 1.130. CRC-related registers Rev.2.00 Oct 16, 2006 page 178 of 264 REJ03B0005-0200 ...
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M30245 Group b15 (1) Setting 0000 16 (2) Setting 01 16 b15 The code resulting from sending 1), becomes the remainder resulting from dividing (1000 0000) X conformity with the ...
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M30245 Group Programmable I/O ports There are 83 programmable I/O ports P10 (excluding P8 output using the direction register. A pull-up resistance for each block of 4 ports can be set. P8 and has no built-in pull-up resistance. ...
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M30245 Group , ...
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M30245 Group Figure 1.133. Programmable I/O ports (2) Rev.2.00 Oct 16, 2006 ...
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M30245 Group Data bus P8 7 Data bus P8 6 Data bus P9 0 Data bus Figure 1.134. Programmable I/O ports (3) Rev.2.00 Oct 16, 2006 page 183 of 264 REJ03B0005-0200 Pull-up selection ...
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M30245 Group P9 2 Data bus P10 to P10 0 7 Data bus Figure 1.135. Programmable I/O ports (4) BYTE BYTE signal input CNV SS CNV RESET RESET signal input Note 1: Note 2: A parasitic diode on the V ...
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M30245 Group Port Pi direction register (Note Port P8 direction register Port P9 direction register Figure ...
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M30245 Group Port Pi register (Note Port P8 register Port P9 register Figure 1.138. Port registers Rev.2.00 Oct ...
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M30245 Group Pull-up control register 0 (Note Pull-up control register Pull-up control register Figure 1.139. Pull-up control registers Rev.2.00 Oct ...
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M30245 Group Port 7 drive capacity register Figure 1.140. High drive capacity register Port control register Figure 1.141. Port control register Table 1.64. Example connection of unused pins in single-chip ...
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M30245 Group Table 1.65. Example connection of unused pins in memory expansion mode Pin name P6 to P10 (excluding /CS1 to P4 /CS3 5 7 BHE, ALE, HLDA, X (Note 1), BCLK OUT HOLD, RDY, NMI ...
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M30245 Group AND Flash Control Circuit The AND flash control circuit is used for communicating with external AND type flash memory devices. The AND flash control circuit can be used only in single-chip mode. This circuit cannot be emulated by ...
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M30245 Group Figure 1.144 shows an example of how to connect an AND type flash memory to the M30245 AND Flash Conntrol circuit. Figure 1.144. Example connections to AND flash memory Table 1.66. AND flash function table WECTL, OECTL AND_OE ...
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M30245 Group Figure 1.145. AND flash read algorithm Figure 1.146. AND flash write algorithm Rev.2.00 Oct 16, 2006 page 192 of 264 REJ03B0005-0200 Start Select External Flash Memory Mode: Command Mode Release Data Read Mode Mode: Write Command/Address Mode Write ...
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M30245 Group Sample AND Flash Code Figures 1.147 and 1.148 show sample code segments of AND flash read and write (program) assembly routines. ; Test Read Access to AND Flash ; MOV.B #03EH, P1 MOV.B #07FH, PD1 MOV.B #00AH, PCR ...
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M30245 Group ; Test Write Access to AND Flash ; MOV.B MOV.B MOV.B MOV.B BCLR BCLR BSET BSET MOV.B BSET MOV.B MOV.B MOV.B MOV.B BCLR RYBY03: BTST JNE RYBY13: BTST JEQ BCLR MOV.W #$0000H, A0 TRANSDATA: MOV.B CMP.W #0083FH, A0 ...
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M30245 Group Flash memory The M30245FC contains flash memory that can be rewritten with a single voltage of 3.3 V. Three flash memory modes are available to read, program, and erase: • CPU rewrite mode in which the flash memory ...
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M30245 Group Table 1.67. M30245 Flash Memory Overview Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division User ROM area Boot ROM area Program method Erase method Program/erase control method Protect method Number of commands Program/erase ...
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M30245 Group CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be read, programmed, or erased under control of the Central Processing Unit (CPU). Only the user ROM area, shown in Figure 1.149, can be rewritten. The ...
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M30245 Group Flash memory control register Figure 1.150. Flash memory control register Single-chip mode, memory expansion Set processor mode register (Note 1) Jump to transferred control program in RAM (Subsequent operations are ...