M30622F8PGP#U3C Renesas Electronics America, M30622F8PGP#U3C Datasheet - Page 24
![IC M16C MCU FLASH 64K 100LQFP](/photos/12/29/122902/m30622f8pgp_u3c_sml.jpg)
M30622F8PGP#U3C
Manufacturer Part Number
M30622F8PGP#U3C
Description
IC M16C MCU FLASH 64K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30622F8PGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30622F8PGP#U3CM30622F8PGP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PGP#U3CM30622F8PGP#D5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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1.4 Flag Register (FLG)
Chapter 1 Overview
Figure 1.4.1 shows a configuration of the flag register (FLG). The function of each flag is detailed below.
1.4.1 Bit 0: Carry flag (C flag)
1.4.2 Bit 1: Debug flag (D flag)
1.4.3 Bit 2: Zero flag (Z flag)
1.4.4 Bit 3: Sign flag (S flag)
1.4.5 Bit 4: Register bank select flag (B flag)
1.4.6 Bit 5: Overflow flag (O flag)
1.4.7 Bit 6: Interrupt enable flag (I flag)
1.4.8 Bit 7: Stack pointer select flag (U flag)
1.4.9 Bits 8-11: Reserved area
This flag holds a carry, borrow, or shifted-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is set (= 1), a single-step interrupt is generated after an instruction is executed. When an
interrupt is acknowledged, this flag is cleared to 0.
This flag is set when an arithmetic operation resulted in 0; otherwise, this flag is 0.
This flag is set when an arithmetic operation resulted in a negative value; otherwise, this flag is 0.
This flag selects a register bank. If this flag is 0, register bank 0 is selected; if the flag is 1, register bank
1 is selected.
This flag is set when an arithmetic operation resulted in overflow.
This flag enables a maskable interrupt.
When this flag is 0, the interrupt is disabled; when the flag is 1, the interrupt is enabled. When the
interrupt is acknowledged, this flag is cleared to 0.
When this flag is 0, the interrupt stack pointer (ISP) is selected; when the flag is 1, the user stack pointer
(USP) is selected.
This flag is cleared to 0 when a hardware interrupt is acknowledged or an INT instruction of software
interrupt numbers 0 to 31 is executed.
6
1.4 Flag Register (FLG)
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