HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 44

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 CPU
1.6.5
(1) Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 1.4. Each instruction uses a
subset of these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-counter
relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or
absolute (8-bit) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT,
and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the
operand.
Table 1.4
No.
1
2
3
4
5
6
7
8
1 Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of a memory operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction is added to an address register (an extended register
paired with a general register) specified by the register field of the instruction, and the lower 24
bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended
when added.
Rev. 3.00 Dec 13, 2004 page 28 of 258
REJ09B0213-0300
Addressing Modes and Effective Address Calculation
Addressing Mode
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
Addressing Modes
Symbol
Rn
@ERn
@(d:16,ERn)/@(d:24,ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24
#xx:8/#xx:16/#xx:32
@(d:8,PC)/@(d:16,PC)
@@aa:8