C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 174

• Manufacturer Part Number: C8051F365-GM
• Description: IC 8051 MCU 32K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F365-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• Package: 28QFN
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1647

C8051F360/1/2/3/4/5/6/7/8/9
174
Bits 7–6: RESERVED. Read = 00b. Must Write 00b.
Bits 5–4: CLKDIV1-0: Output SYSCLK Divide Factor.
Bit 3:
Bits 2–0: CLKSL2–0: System Clock Source Select Bits.
SFR Page:
SFR Address:
Reserved Reserved CLKDIV1 CLKDIV0 Reserved CLKSL2
R/W
Bit7
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the
crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See Section “17. Port Input/Output” on page 183 for more details about routing this output to
a port pin.
RESERVED. Read = 0b. Must Write 0b.
000: SYSCLK derived from the high-frequency Internal Oscillator, and scaled as per the
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the low-frequency Internal Oscillator, and scaled as per the
011: RESERVED.
100: SYSCLK derived from the PLL.
101-11x: RESERVED.
F
0x8F
IFCN bits in OSCICN.
OSCLD bits in OSCLCN.
R/W
Bit6
SFR Definition 16.4. CLKSEL: System Clock Selection
R/W
Bit5
R/W
Bit4
Rev. 1.0
R/W
Bit3
R/W
Bit2
CLKSL1
R/W
Bit1
CLKSL0 00000000
R/W
Bit0
Reset Value