C8051T601-GM Silicon Laboratories Inc, C8051T601-GM Datasheet - Page 50

IC 8051 MCU 8K-EEPROM 11-QFN

C8051T601-GM

Manufacturer Part Number
C8051T601-GM
Description
IC 8051 MCU 8K-EEPROM 11-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet

Specifications of C8051T601-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
8
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
336-1652-5
C8051T600/1/2/3/4/5/6
9.5. ADC0 Analog Multiplexer (C8051T600/2/4 only)
ADC0 on the C8051T600/2/4 uses an analog input multiplexer to select the positive input to the ADC. Any
of the following may be selected as the positive input: Port 0 I/O pins, the on-chip temperature sensor, or
the positive power supply (V
SFR Definition 9.9.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set the corresponding bit in register PnMDIN to ‘0’. To force the Crossbar to skip a Port pin, set the
corresponding bit in register XBR0 to ‘1’. See Section “22. Port Input/Output” on page 106 for more Port
I/O configuration details.
50
Sensor
Temp
Figure 9.6. ADC0 Multiplexer Block Diagram
DD
). The ADC0 input channel is selected in the AMX0SL register described in
P0.0
P0.7
VDD
AMX0SL
Rev. 1.2
AMUX
ADC0

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