C8051T604-GS Silicon Laboratories Inc, C8051T604-GS Datasheet - Page 40
C8051T604-GS
Manufacturer Part Number
C8051T604-GS
Description
IC 8051 MCU 2K-EEPROM 14-SOIC
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T604-GS
Program Memory Type
OTP
Program Memory Size
2KB (2K x 8)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SMBus/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1659-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T604-GS
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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C8051T600/1/2/3/4/5/6
9. 10-Bit ADC (ADC0, C8051T600/2/4 only)
ADC0 on the C8051T600/2/4 is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector.
The ADC is fully configurable under software control via Special Function Registers. The ADC may be con-
figured to measure various different signals using the analog multiplexer described in Section “9.5. ADC0
Analog Multiplexer (C8051T600/2/4 only)” on page 50. The voltage reference for the ADC is selected as
described in Section “11. Voltage Reference Options” on page 55. The ADC0 subsystem is enabled only
when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in
low power shutdown when this bit is logic 0.
40
AMUX0
From
X1 or
X0.5
AMP0GN0
Figure 9.1. ADC0 Functional Block Diagram
AIN
ADC0CF
ADC
10-Bit
VDD
SAR
Rev. 1.2
ADC0GTH ADC0GTL
ADC0LTH
ADC0CN
ADC0LTL
Conversion
Start
000
001
010
011
100
101
32
AD0WINT
Compare
Window
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
Logic
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