Z8F022ASJ020SC Zilog, Z8F022ASJ020SC Datasheet - Page 35
![IC ENCORE XP MCU FLASH 2K 28SOIC](/photos/6/91/69136/269-28-soic_sml.jpg)
Z8F022ASJ020SC
Manufacturer Part Number
Z8F022ASJ020SC
Description
IC ENCORE XP MCU FLASH 2K 28SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F022ASJ020SC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
23
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3355
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F022ASJ020SC
Manufacturer:
Zilog
Quantity:
372
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Table 8. Reset and Stop Mode Recovery Characteristics and Latency
PS022825-0908
Reset Type
System Reset
System Reset with Crystal
Oscillator Enabled
Stop Mode Recovery
Stop Mode Recovery with
Crystal Oscillator Enabled
During a System Reset or Stop Mode Recovery, the Internal Precision Oscillator requires
4
cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash
option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because
of a low voltage condition or Power-On Reset (POR), this delay is measured from the time
that the supply voltage first exceeds the POR level. If the external pin reset remains
asserted at the end of the reset period, the device remains in reset until the pin is deas-
serted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 (or PA2 on 8-pin devices) which is shared with the reset pin. On reset,
the PD0 is configured as a bidirectional open-drain reset. The pin is internally driven low
during port reset, after which the user code may reconfigure this pin as a general purpose
output.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer,
Register Pointer, and Flags) and general-purpose RAM are undefined following Reset.
The eZ8 CPU fetches the Reset vector at Program Memory addresses
and loads that value into the Program Counter. Program execution begins at the Reset
vector address.
As the control registers are re-initialized by a system reset, the system clock after reset is
always the IPO. The software must reconfigure the oscillator control block, such that the
correct system clock source is enabled and selected.
µ
s to start up. Then the Z8 Encore! XP F082A Series device is held in Reset for 66
Control Registers
Reset (as applicable)
Reset (as applicable)
Unaffected, except
WDT_CTL and
OSC_CTL registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
Reset Characteristics and Latency
Reset 66 Internal Precision Oscillator Cycles
Reset 5000 Internal Precision Oscillator Cycles
Reset 66 Internal Precision Oscillator Cycles
Reset 5000 Internal Precision Oscillator Cycles
Reset, Stop Mode Recovery, and Low Voltage Detection
CPU
eZ8
Reset Latency (Delay)
+ IPO startup time
Z8 Encore! XP
Product Specification
0002H
®
F082A Series
and
0003H
24
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