PIC16LC77-04I/L Microchip Technology, PIC16LC77-04I/L Datasheet - Page 96
![IC MCU OTP 8KX14 A/D PWM 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16LC77-04I/L
Manufacturer Part Number
PIC16LC77-04I/L
Description
IC MCU OTP 8KX14 A/D PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC77-04I/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
OTP
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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PIC16C7X
11.5.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 11-26).
FIGURE 11-26: I
DS30390E-page 96
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
TRANSMISSION
A7
1
Data in
sampled
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A6
2
A5
Receiving Address
3
A4
4
A3
5
A2
6
A1
7
R/W = 1
8
72 73 73A 74 74A 76 77
Applicable Devices
9
ACK
responds to SSPIF
SCL held low
while CPU
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave then monitors for
another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR reg-
ister. Then pin RC3/SCK/SCL should be enabled by
setting bit CKP.
D7
1
SSPBUF is written in software
D6
2
cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D5
3
D4
4
Transmitting Data
D3
5
1997 Microchip Technology Inc.
D2
6
From SSP interrupt
service routine
D1
7
D0
8
ACK
9
P
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