PIC16C66-04/SP Microchip Technology, PIC16C66-04/SP Datasheet - Page 115

• Manufacturer Part Number: PIC16C66-04/SP
• Description: IC MCU OTP 8KX14 PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C66-04/SP

• Program Memory Type: OTP
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 368Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
TABLE 12-7:
Address Name
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: PSPIE and PSPIF are reserved on the PIC16C63/R63/66, always maintain these bits clear.
1997 Microchip Technology Inc.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 12.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting enable bit
CREN.
2: PIE1<6> and PIR1<6> are reserved, always maintain these bits clear.
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
(1)
(1)
Bit 6
RX9
TX9
(2)
(2)
SREN
TXEN
RCIF
RCIE
Bit 5
CREN
SYNC
TXIE
Bit 4
TXIF
SSPIE CCP1IE TMR2IE
SSPIF CCP1IF
Bit 3
—
—
6.
7.
8.
9.
BRGH
FERR
Bit 2
Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
TMR2IF
OERR
TRMT
Bit 1
TMR1IF
TMR1IE
RX9D
TX9D
Bit 0
PIC16C6X
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
POR,
BOR
DS30234D-page 115
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
all other
Resets