DSPIC33FJ32MC204-I/ML Microchip Technology, DSPIC33FJ32MC204-I/ML Datasheet - Page 6

• Manufacturer Part Number: DSPIC33FJ32MC204-I/ML
• Description: IC DSPIC MCU/DSP 32K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC204-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-QFN
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330017
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
13. Module: UART
14. Module: Internal Voltage Regulator
DS80463E-page 6
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
When the VREGS bit (RCON<8>) is set to a logic
‘0’, device may Reset and higher sleep current
may be observed.
Work around
Ensure VREGS bit (RCON<8>) is set to a logic ‘1’
for device Sleep mode operation.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
A4
A4
X
X
A5
A5
X
X
A6
A6
X
X
15. Module: PSV Operations
16. Module: I
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register indirect addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
A2
A2
mode) with pre/post-decrement
X
X
A3
A3
X
X
than
2
2
C
C module is configured as a 10-bit
A4
A4
X
X
0x02;
© 2010 Microchip Technology Inc.
A5
A5
X
X
however,
A6
A6
X
X
the
module