PIC24HJ32GP202-I/MM Microchip Technology, PIC24HJ32GP202-I/MM Datasheet - Page 21
![IC PIC MCU FLASH 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24HJ32GP202-I/MM
Manufacturer Part Number
PIC24HJ32GP202-I/MM
Description
IC PIC MCU FLASH 32K 28QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ32GP204-IML.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.6.2
Configuration bits may be programmed a single byte at
a time using the PROGC command. This command
specifies the configuration data and Configuration
register address.
Twelve PROGC commands are required to program all
the Configuration bits. A flowchart for Configuration bit
programming is illustrated in
FIGURE 3-5:
© 2010 Microchip Technology Inc.
Note:
Note 1: For dsPIC33FJ06GS101/102/202, dsPIC33FJ16GS402/404/502/504, dsPIC33FJ32GS406/606/608/610 and
PROGRAMMING METHODOLOGY
If either of the General Code Segment
Code-Protect
programmed to ‘0’, code memory is
code-protected and cannot be read.
Code memory must be verified before
enabling
Section 3.6.4 “CodeGuard™ Security
Configuration
information
Configuration bits.
dsPIC33FJ64GS406/606/608/610 devices, the Configuration address is 0xF80014.
ConfigAddress + 2
ConfigAddress =
CONFIGURATION BIT PROGRAMMING FLOW
read
bits
Figure
about
Bits”
protection.
3-5.
(GSS<1:0>)
for
code-protect
detailed
No
See
is
PROGC response
ConfigAddress
0xF80018?
Send PROGC
Command
PASS?
Start
3.6.3
After the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READC command reads back the programmed
Configuration bits and verifies that the programming
was successful.
Any unimplemented Configuration bits are read-only
and read as ‘0’. The reserved bits are read-only and
read as ‘1’.
End
Is
Is
Yes
Yes
(1)
ConfigAddress = 0xF80000
PROGRAMMING VERIFICATION
No
Report Error
Failure
DS70152H-page 21