PIC24HJ32GP202-I/MM Microchip Technology, PIC24HJ32GP202-I/MM Datasheet - Page 178
![IC PIC MCU FLASH 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24HJ32GP202-I/MM
Manufacturer Part Number
PIC24HJ32GP202-I/MM
Description
IC PIC MCU FLASH 32K 28QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ32GP204-IML.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- PIC24HJ32GP204-IML PDF datasheet #5
- Current page: 178 of 244
- Download datasheet (4Mb)
PIC24HJ32GP202/204 and PIC24HJ16GP304
18.2
All
PIC24HJ16GP304 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices
PIC24HJ16GP304 family incorporate an on-chip regu-
lator that allows the device to run its core logic from
V
The regulator provides power to the core from the other
V
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure 18-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section TABLE 21-13: “Internal
Voltage
Section 21.1 “DC Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 18-1:
18.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated voltage V
module is to generate a device Reset when a brown-
out condition occurs. Brown-out conditions are gener-
ally caused by glitches on the AC mains (for example,
missing portions of the AC cycle waveform due to bad
power transmission lines, or voltage sags due to exces-
sive current draw when a large inductive load is turned
on).
DS70289A-page 176
DD
DD
Note 1:
.
pins. When the regulator is enabled, a low-ESR
of
On-Chip Voltage Regulator
BOR: Brown-Out Reset
,
Regulator
STARTUP
in
it takes approximately 20 μs for the on-chip
C
F
These are typical operating voltages. Refer
to Section TABLE 21-13: “Internal Volt-
age Regulator Specifications” located in
Section 21.1 “DC Characteristics” for the
full operating ranges of V
the
3.3V
DDCORE
the
is applied every time the device
PIC24HJ32GP202/204
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
Specifications”
PIC24HJ32GP202/204
. The main purpose of the BOR
DD
DDCORE
SS
PIC24H
STARTUP
/V
CAP
, code execution is
DD
DDCORE
and V
(1)
located
DDCORE
/V
CAP
.
and
and
Preliminary
pin
in
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If TPWRT
= 0 and a crystal oscillator is being used, a nominal
delay of TFSCM = 100 is applied. The total delay in this
case is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that
a BOR has occurred. If the BOR circuit is enabled, it
continues to operate while in Sleep or Idle mode and
resets the device in case VDD falls below the BOR
threshold voltage.
© 2007 Microchip Technology Inc.
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