PIC24HJ32GP202-I/MM Microchip Technology, PIC24HJ32GP202-I/MM Datasheet - Page 39
PIC24HJ32GP202-I/MM
Manufacturer Part Number
PIC24HJ32GP202-I/MM
Description
IC PIC MCU FLASH 32K 28QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ32GP204-IML.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- PIC24HJ32GP204-IML PDF datasheet #5
- Current page: 39 of 272
- Download datasheet (4Mb)
TABLE 4-20:
TABLE 4-21:
TABLE 4-22:
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
Legend:
File Name
File Name
File Name
1:
2:
1:
Addr
0740
0742
0744
0746
0748
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
0770
0772
0760
0766
SYSTEM CONTROL REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
TRAPR
Bit 15
IC8MD
Bit 15
ROI
Bit 15
—
—
—
WR
—
—
IOPUWR
IC7MD
Bit 14
Bit 14
WREN
Bit 14
—
—
—
—
COSC<2:0>
DOZE<2:0>
Bit 13
T3MD
Bit 13
WRERR
Bit 13
—
—
—
—
—
Bit 12
T2MD
Bit 12
—
—
—
—
Bit 12
—
—
DOZEN
Bit 11
T1MD
Bit 11
—
—
—
—
—
Bit 11
—
—
Bit 10
Bit 10
—
—
—
—
—
Bit 10
—
—
FRCDIV<2:0>
NOSC<2:0>
IC2MD
Bit 9
Bit 9
CM
—
—
—
Bit 9
—
—
VREGS
IC1MD
Bit 8
Bit 8
—
—
Bit 8
—
—
CLKLOCK IOLOCK
I2C1MD
EXTR
Bit 7
PLLPOST<1:0>
Bit 7
—
—
Bit 7
—
Bit 6
SWR
Bit 6
—
ERASE
—
—
Bit 6
SWDTEN
LOCK
Bit 5
U1MD
Bit 5
—
—
Bit 5
—
PLLDIV<8:0>
WDTO
Bit 4
—
Bit 4
Bit 4
—
—
NVMKEY<7:0>
—
SLEEP
SPI1MD
Bit 3
CF
Bit 3
Bit 3
—
TUN<5:0>
PLLPRE<4:0>
Bit 2
IDLE
—
Bit 2
Bit 2
—
—
NVMOP<3:0>
LPOSCEN
OC2MD
Bit 1
BOR
Bit 1
Bit 1
—
OSWEN
AD1MD
OC1MD
Bit 0
POR
Bit 0
Bit 0
Resets
Resets
Resets
xxxx
0300
3040
0030
0000
0000
0000
0000
0000
All
All
All
(1)
(2)
(1)
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