PIC18F66J90-I/PT Microchip Technology, PIC18F66J90-I/PT Datasheet - Page 433
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PIC18F66J90-I/PT
Manufacturer Part Number
PIC18F66J90-I/PT
Description
IC PIC MCU FLASH 64KB 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F67J90-IPT.pdf
(450 pages)
2.PIC18F67J90-IPT.pdf
(3 pages)
3.PIC18F67J90-IPT.pdf
(10 pages)
4.PIC18F66J90-IPT.pdf
(444 pages)
Specifications of PIC18F66J90-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Operating Supply Voltage
2.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163030
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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Compare (CCP Module) ................................................... 171
Computed GOTO ................................................................ 63
Configuration Bits.............................................................. 319
Configuration Mismatch (CM) ............................................. 49
Configuration Register Protection ..................................... 332
Core Features
CPFSEQ ........................................................................... 350
CPFSGT ........................................................................... 351
CPFSLT ............................................................................ 351
Crystal Oscillator/Ceramic Resonator ................................. 33
Customer Change Notification Service ............................. 439
Customer Notification Service........................................... 439
Customer Support ............................................................. 439
D
Data Addressing Modes...................................................... 76
Data Memory ...................................................................... 66
DAW.................................................................................. 352
DC Characteristics ............................................................ 398
DCFSNZ ........................................................................... 353
DECF ................................................................................ 352
DECFSZ............................................................................ 353
Default System Clock.......................................................... 32
Details on Individual Family Members .................................. 8
Development Support ....................................................... 383
Device Overview ................................................................... 7
Direct Addressing................................................................ 77
E
Effect on Standard PIC18 Instructions .............................. 380
Effects of Power-Managed Modes on Various
Electrical Characteristics................................................... 387
© 2009 Microchip Technology Inc.
Associated Registers ................................................ 172
CCP Pin Configuration.............................................. 171
CCPR2 Register ....................................................... 171
Software Interrupt ..................................................... 171
Special Event Trigger................................ 147, 171, 290
Timer1/Timer3 Mode Selection................................. 171
Easy Migration .............................................................. 7
Extended Instruction Set............................................... 7
Memory Options............................................................ 7
nanoWatt Technology ................................................... 7
Oscillator Options and Features ................................... 7
Comparing Addressing Modes with the
Direct........................................................................... 76
Indexed Literal Offset.................................................. 79
Indirect ........................................................................ 76
Inherent and Literal ..................................................... 76
Access Bank ............................................................... 68
Bank Select Register (BSR)........................................ 66
Extended Instruction Set............................................. 79
General Purpose Registers......................................... 68
Memory Maps
Special Function Registers ......................................... 69
Power-Down and Supply Current ............................. 390
Supply Voltage.......................................................... 389
Features (64-Pin Devices) ............................................ 9
Features (80-Pin Devices) ............................................ 9
Clock Sources............................................................. 37
Extended Instruction Set Enabled ...................... 80
BSR .................................................................... 81
Instructions Affected ........................................... 79
Mapping Access Bank ........................................ 81
PIC18FX6J90/X7J90 Devices ............................ 67
Special Function Registers ................................. 69
Preliminary
PIC18F87J90 FAMILY
Enhanced Universal Synchronous Asynchronous
ENVREG Pin .................................................................... 328
Equations
Errata .................................................................................... 6
EUSART
Extended Instruction Set
External Oscillator Modes
F
Fail-Safe Clock Monitor ............................................ 319, 330
Fast Register Stack ............................................................ 63
Firmware Instructions ....................................................... 333
Flash Configuration Words ............................................... 319
Flash Program Memory ...................................................... 83
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 288
A/D Minimum Charging Time ................................... 288
Calculating the Minimum Required
LCD Static and Dynamic Current ............................. 187
Asynchronous Mode................................................. 258
Baud Rate Generator (BRG) .................................... 253
Synchronous Master Mode....................................... 264
Synchronous Slave Mode......................................... 267
ADDFSR................................................................... 376
ADDULNK ................................................................ 376
CALLW ..................................................................... 377
MOVSF..................................................................... 377
MOVSS..................................................................... 378
PUSHL...................................................................... 378
SUBFSR ................................................................... 379
SUBULNK................................................................. 379
Clock Input (EC Modes) ............................................. 34
HS............................................................................... 33
Exiting Fail-Safe Operation....................................... 331
Interrupts in Power-Managed Modes ....................... 331
POR or Wake-up From Sleep................................... 331
WDT During Oscillator Failure.................................. 330
Associated Registers.................................................. 92
Control Registers........................................................ 84
Erase Sequence ......................................................... 88
Acquisition Time ............................................... 288
12-Bit Break Transmit and Receive.................. 263
Associated Registers, Receive......................... 261
Associated Registers, Transmit........................ 259
Auto-Wake-up on Sync Break Character ......... 262
Receiver ........................................................... 260
Setting up 9-Bit Mode with Address Detect ...... 260
Transmitter ....................................................... 258
Associated Registers........................................ 253
Auto-Baud Rate Detect..................................... 256
Baud Rate Error, Calculating............................ 253
Baud Rates, Asynchronous Modes .................. 254
High Baud Rate Select (BRGH Bit) .................. 253
Operation in Power-Managed Modes............... 253
Sampling .......................................................... 253
Associated Registers, Receive......................... 266
Associated Registers, Transmit........................ 265
Reception ......................................................... 266
Transmission .................................................... 264
Associated Registers, Receive......................... 268
Associated Registers, Transmit........................ 267
Reception ......................................................... 268
Transmission .................................................... 267
EECON1 and EECON2 ...................................... 84
TABLAT (Table Latch) Register ......................... 86
TBLPTR (Table Pointer) Register....................... 86
DS39933C-page 431
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