PIC24FJ32GA002-E/ML Microchip Technology, PIC24FJ32GA002-E/ML Datasheet - Page 147
![IC PIC MCU FLASH 32K 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ32GA002-E/ML
Manufacturer Part Number
PIC24FJ32GA002-E/ML
Description
IC PIC MCU FLASH 32K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA004-EPT.pdf
(262 pages)
Specifications of PIC24FJ32GA002-E/ML
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ32GA002-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC24FJ32GA002-E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- PIC24FJ64GA004-EPT PDF datasheet #4
- Current page: 147 of 262
- Download datasheet (5Mb)
15.3
To compute the Baud Rate Generator reload value, use
Equation 15-1.
EQUATION 15-1:
TABLE 15-1:
TABLE 15-2:
© 2008 Microchip Technology Inc.
Note 1:
Note 1:
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
Note 1: Based on F
Address
Slave
2:
3:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
Setting Baud Rate When
Operating as a Bus Master
1 MHz
1 MHz
1 MHz
F
I2CxBRG
F
The address bits listed here will never cause an address match, independent of the address mask settings.
Address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
SCL
or
Based on F
SCL
PLL are disabled.
=
R/W
Bit
I
I
0
1
x
x
x
x
x
x
2
2
--------------------------------------------------------------------- -
I2CxBRG
C™ CLOCK RATES
C™ RESERVED ADDRESSES
=
COMPUTING BAUD RATE
RELOAD VALUE
⎛
⎝
CY
CY
----------- -
F
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte
F
SCL
CY
= F
= F
+ +
–
OSC
F
OSC
1
----------------------------- -
10 000 000
CY
16 MHz
16 MHz
16 MHz
,
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and PLL are disabled.
----------------------------- -
10 000 000
/2; Doze mode and
F
F
CY
CY
,
,
F
CY
,
⎞
⎠
(1)
(1)
–
1
(2)
(3)
PIC24FJ64GA004 FAMILY
Preliminary
(Decimal)
(1)
157
78
39
37
18
13
9
4
6
3
I2CxBRG Value
15.4
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Description
Note:
(Hexadecimal)
Slave Address Masking
As a result of changes in the I
col, the addresses in Table 15-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
9D
4E
27
25
12
D
9
4
6
3
1.026 MHz
1.026 MHz
0.909 MHz
DS39881C-page 145
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
Actual
99 kHz
F
SCL
2
C™ proto-
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