PIC24HJ12GP202-I/ML Microchip Technology, PIC24HJ12GP202-I/ML Datasheet
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... Microchip Technology Inc. PIC24HJ12GP201/202 High-Performance, 16-Bit Microcontrollers Preliminary Data Sheet DS70282B ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
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... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN Note: See the device variant tables for exact peripheral features per device. Preliminary © 2007 Microchip Technology Inc. ...
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... The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES Device PIC24HJ12GP201 18 12 PIC24HJ12GP202 28 12 Note 1: Only 2 out of 3 timers are remappable. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Remappable Peripherals (1) ...
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... OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSC/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5/CN27/RB5 DS70282B-page 4 MCLR AN6/RP15/CN11/RB15 3 16 AN7/RP14/CN12/RB14 DDCORE SCL1/RP9/CN21/RB9 SDA1/RP8/CN22/RB8 11 9 INT0/RP7/CN23/RB7 10 MCLR AN6/RP15/CN11/RB15 3 26 AN7/RP14/CN12/RB14 4 25 AN8/RP13/CN13/RB13 AN9/RP12/CN14/RB12 23 7 TMS/RP11/CN15/RB11 22 Vss TDI/RP10/CN16/RB10 DDCORE 10 Vss 19 TDO/SDA1/RP9/CN21/RB9 11 18 TCK/SCL1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 DD 16 ASCL1/RP6/CN24/RB6 14 15 Preliminary © 2007 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 28-Pin QFN PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 PIC24HJ12GP202 Preliminary AN8/RP13/CN13/RB13 AN9/RP12/CN14/RB12 TMS/RP11/CN15/RB11 TDI/RP10/CN16/RB10 V DDCORE V SS TDO/SDA1/RP9/CN21/RB9 DS70282B-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70282B-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... Reference Manual chapters. This document contains device specific information for the following devices: • PIC24HJ12GP201 • PIC24HJ12GP202 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. ...
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... DS70282B-page 8 Data Bus Data Latch X RAM Address Loop Latch Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR UART1 CNx SPI1 I2C1 Preliminary PORTA PORTB 16 Remappable Pins © 2007 Microchip Technology Inc. ...
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... PGC3/EMUC3 I ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2007 Microchip Technology Inc. ...
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... A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model PIC24HJ12GP201/202 is shown in Figure 2-2. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 2.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). ...
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... Control Signals to Various Blocks DS70282B-page 12 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...
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... FIGURE 2-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
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... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70282B-page 14 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
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... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. Preliminary © 2007 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.1 Program Address Space The program PIC24HJ12GP201/202 devices is 4M instructions ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary devices reserve the PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2007 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70282B-page 20 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 0x1FFFF 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2007 Microchip Technology Inc. ...
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TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 3-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 3-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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... RPINR21 06AA — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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TABLE 3-14: ADC1 REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... TABLE 3-15: ADC1 REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-17: PORTB REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 TRISB13 ...
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TABLE 3-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.2.6 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...
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... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary © 2007 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70282B-page 34 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2007 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2007 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions ...
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... WR bit is automatically cleared when the operation is finished. required for Preliminary the user application must to Section 4.4 “Programming finished. Setting the WR bit © 2007 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 — — (1) ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70282B-page 40 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2007 Microchip Technology Inc. ...
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... Regulator Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Any active source of Reset makes the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
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... SWDTEN bit setting. DS70282B-page 44 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note 1: All Reset flag bits may be set or cleared by the user software. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 (1) (1) Setting Event Trap conflict event Illegal opcode or uninitialized W register access Configuration mismatch ...
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... RST T — RST T — RST T — RST T — RST is also applied to all returns from powered-down STARTUP Preliminary FSCM Notes Delay — FSCM FSCM LOCK FSCM — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — 3 © 2007 Microchip Technology Inc. ...
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... FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 48 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ12GP201/202 devices implement unique interrupts and 4 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1 ...
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... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70282B-page 50 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24HJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2007 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 6.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt ...
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... The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> DS70282B-page 54 (1) U-0 U-0 — — (3) R-0 R/W-0 ( Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... CPU interrupt priority level less Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS70282B-page 56 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — ...
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... Interrupt request has not occurred DS70282B-page 58 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 59 ...
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... Interrupt request has not occurred DS70282B-page 60 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request not enabled DS70282B-page 62 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 63 ...
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... Interrupt request not enabled DS70282B-page 64 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70282B-page 66 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70282B-page 68 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70282B-page 70 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
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... Unimplemented: Read as ‘0’ DS70282B-page 72 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70282B-page 74 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
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... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 76 Preliminary © 2007 Microchip Technology Inc. ...
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... Secondary Oscillator SOSCO LPOSCEN SOSCI Note 1: See Figure 7-2 for PLL details © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed ...
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... This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either and PLL must be selected such that the PLL output frequency ( the range of 12.5 MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. Preliminary © 2007 Microchip Technology Inc. Configuration bits, is divided OSC ). ...
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... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 ’, • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a IN VCO output 160 MHz, which is within the 100-200 MHz ranged needed. • ...
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... Unimplemented: Read as ‘0’ DS70282B-page 80 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 83
... OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 81 ...
Page 84
... This bit is cleared when the ROI bit is set and an interrupt occurs. DS70282B-page 82 R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 85
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 86
... Center frequency -12% (6.49 MHz) DS70282B-page 84 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 87
... Set the OSWEN bit to initiate the oscillator switch. Once the basic sequence is completed, the system clock hardware responds automatically as follows: © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation ...
Page 88
... PIC24HJ12GP201/202 NOTES: DS70282B-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 8.2 Instruction-Based Power-Saving Modes PIC24HJ12GP201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 90
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible © 2007 Microchip Technology Inc. ...
Page 91
... CK WR Port Data Latch Read LAT Read Port © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled ...
Page 92
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary © 2007 Microchip Technology Inc. ...
Page 93
... I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...
Page 94
... RPINR7 IC2 RPINR7 IC7 RPINR10 IC8 RPINR10 OCFA RPINR11 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1IN RPINR20 SS1IN RPINR21 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> © 2007 Microchip Technology Inc. ...
Page 95
... SDO1 SCK1OUT SS1OUT OC1 OC2 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of ‘ ...
Page 96
... Because the unlock sequence is timing critical, it must be executed as an assembly language routine, in the same manner as changes configuration. If the bulk of the application is written another high-level language, the unlock sequence should be performed by writing inline assembly. Preliminary © 2007 Microchip Technology Inc. to the oscillator ...
Page 97
... Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 EXAMPLE 9-2: //************************************* // Unlock Registers //************************************* asm volatile ( " ...
Page 98
... Unimplemented: Read as ‘0’ DS70282B-page 96 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R< ...
Page 100
... Input tied to RP1 00000 = Input tied to RP0 DS70282B-page 98 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R< ...
Page 102
... Input tied to RP1 00000 = Input tied to RP0 DS70282B-page 100 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 103
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR< ...
Page 104
... Input tied to RP1 00000 = Input tied to RP0 DS70282B-page 102 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 105
... SDI1R<4:0>: Assign SPI 1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R< ...
Page 106
... Input tied to RP0 DS70282B-page 104 U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 107
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 9-2 for periph- eral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-2 for periph- eral function numbers) © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 ...
Page 108
... Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 109
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 ...
Page 110
... Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 111
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS< ...
Page 112
... DS70282B-page 110 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 113
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is gener- ated with the Timer3 interrupt flags. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 11.1 32-bit Operation To configure the Timer2/3 feature for 32-bit operation: 1 ...
Page 114
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70282B-page 112 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...
Page 115
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70282B-page 113 ...
Page 116
... DS70282B-page 114 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 117
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 (1) — — R/W-0 ...
Page 118
... PIC24HJ12GP201/202 NOTES: DS70282B-page 116 Preliminary © 2007 Microchip Technology Inc. ...
Page 119
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 • Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin ...
Page 120
... Input capture module turned off DS70282B-page 118 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘100’. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Disabling and re-enabling the timer, and clearing the TMRy register, are not required, but may be advantageous for defining a pulse from a known event time boundary ...
Page 122
... See Example 13-1 for PWM mode timing details. Table 13-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM bits log (2) 10 Preliminary © 2007 Microchip Technology Inc. • (Timer Prescale Value) CY ...
Page 123
... FFFFh Resolution (bits) 16 TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (F PWM Frequency 76 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 Hz ...
Page 124
... OCFA pin controls OC1-OC2 channels. 3: TMR2/TMR3 can be selected via OCTSEL(OCxOCN<3>) bit. DS70282B-page 122 Set Flag bit (1) OCxIF S Q Output Logic R Output Enable 3 OCM2:OCM0 Mode Select 0 1 Period match signals (3) from time bases Preliminary (1) OCx (2) OCFA © 2007 Microchip Technology Inc. ...
Page 125
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 126
... PIC24HJ12GP201/202 NOTES: DS70282B-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... The module will not respond to SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPIxBUF is read by user software. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 14.3 Transmit Operations Transmit writes are also double-buffered. The user application writes to SPIxBUF ...
Page 128
... Control SDOx bit 0 SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF DS70282B-page 126 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 F Primary CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
Page 129
... User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 14-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24H FIGURE 14-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24H © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx ...
Page 130
... Preliminary 4:1 6:1 8:1 6666.67 5000 2500 1666.67 1250 625 416.67 312.50 104.17 78.125 1250 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
Page 131
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 132
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70282B-page 130 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 133
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 131 ...
Page 134
... DS70282B-page 132 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 FRMDLY — bit Bit is unknown ...
Page 135
... Family Reference Manual”. Please see the Microchip (www.microchip.com) for the latest PIC24H Family Reference Manual chapters. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 2 15 Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable ...
Page 136
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
Page 137
... The control bit IPMIEN enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 15.8 General Call Address Support The general call address can address all devices. ...
Page 138
... When the ACTI2C bit in the FPOR configura- tion register is set to ‘1‘, the module uses the SDAx/ SCLx pins. If the ALTI2C bit is ‘0‘, the module uses the ASDAx/ASCLx pins. Preliminary © 2007 Microchip Technology Inc port to its Idle state. ...
Page 139
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 140
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70282B-page 138 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master) Preliminary 2 C master) © 2007 Microchip Technology Inc. ...
Page 141
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 R/C-0 HS — ...
Page 142
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70282B-page 140 2 C slave device address byte. Preliminary © 2007 Microchip Technology Inc. ...
Page 143
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 144
... PIC24HJ12GP201/202 NOTES: DS70282B-page 142 Preliminary © 2007 Microchip Technology Inc. ...
Page 145
... FIGURE 16-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 • Hardware Flow Control Option with UxCTS and UxRTS pins • Fully Integrated Baud Rate Generator with 16-bit prescaler • ...
Page 146
... Desired Baud Rate Preliminary UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate denotes the instruction cycle clock /2). OSC CY © 2007 Microchip Technology Inc. /4 ...
Page 147
... Write 0x55 to UxTXREG, which loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 16.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 16.2 “ ...
Page 148
... DS70282B-page 146 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 149
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 MODE REGISTER (CONTINUED) x Preliminary DS70282B-page 147 ...
Page 150
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 151
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...
Page 152
... PIC24HJ12GP201/202 NOTES: DS70282B-page 150 Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... There is only 1 sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Depending on the particular device pinout, the ADC can have analog input pins, designated AN0 through AN9. In addition, there are two analog input pins for external voltage reference connections ...
Page 154
... Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70282B-page 152 (2) CH1 ADC1 S Conversion Result + (2) CH2 S (2) CH3 S/H CH1,CH2, - CH3,CH0 - Sample Input Switches + CH0 - S/H - Preliminary Conversion Logic 16-bit ADC Output Buffer Sample/Sequence Control Input MUX Control © 2007 Microchip Technology Inc. ...
Page 155
... ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal RC Clock T CY OSC ( Note: Refer to Figure 7-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, F the clock source frequency. T © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 = T (ADCS + – 1 ADCS = – ...
Page 156
... Bit is cleared = ssss sssd dddd dddd, where s = .NOT.d<9>) OUT = ssss sddd dddd dddd, where s = .NOT.d<11>) OUT Preliminary R/W-0 R/W-0 R/W-0 AD12B FORM<1:0> bit 8 R/W-0 R/W-0 R/C-0 HC,HS HC, HS ASAM SAMP DONE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 157
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary ...
Page 158
... R/W-0 R/W-0 SMPI<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ADREF- A VSS + A VSS External V - REF + External V - REF Avss Preliminary R/W-0 R/W-0 R/W-0 CSCNA CHPS<1:0> bit 8 R/W-0 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... T CY • • • 000010 = T · (ADCS<7:0> · 000001 = T · (ADCS<7:0> · 000000 = T · (ADCS<7:0> · © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 ADCS<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = T CY ...
Page 160
... Reserved 01 = Reserved 00 = Reserved If AD12B = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 ...
Page 161
... Reserved 01 = Reserved 00 = Reserved If AD12B = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 ...
Page 162
... Channel 0 positive input is AN5 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 PIC24HJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 163
... Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note 1: On devices without nine analog inputs, all PCFG bits are R/W. However, PCFG bits are ignored on ports without a corresponding input on device. 2: PIC24HJ12GP201 devices support only 6 channels (PCFG0-PCFG5). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 162 Preliminary © 2007 Microchip Technology Inc. ...
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... FUID2 0xF80016 FUID3 Note 1: These reserved bits read as ‘1’ and must be programmed as ‘1’. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 18.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000 ...
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... Allow multiple reconfigurations OSC2 Pin Function bit (except in XT and HS modes OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled Crystal Oscillator mode Crystal Oscillator mode (External Clock) mode Preliminary © 2007 Microchip Technology Inc. ...
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... WDTPOST<3:0> FWDT ALTI2C FPOR FPWRT<2:0> FPOR © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect Watchdog Timer enabled/disabled by user software (LPRC can be ...
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... The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit, if enabled, contin- ues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. and V . DDCORE Preliminary . The main purpose of the BOR DDCORE © 2007 Microchip Technology Inc. ...
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... CLRWDT Instruction SWDTEN FWDTEN LPRC Clock (divide by N1) WINDIS © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 18.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
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... GS = 3584 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 768 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 3072 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 1792 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 2048 IW 001FFEh “CodeGuard™ © 2007 Microchip Technology Inc. ...
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... Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGC1/EMUC1 and PGD1/EMUD1 • PGC2/EMUC2 and PGD2/EMUD2 • PGC3/EMUC3 and PGD3/EMUD3 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 18.8 In-Circuit Debugger ® When MPLAB circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 170 Preliminary © 2007 Microchip Technology Inc. ...
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... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: • ...
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... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). Description Preliminary © 2007 Microchip Technology Inc. ...
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... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Preliminary DS70282B-page 173 ...
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... Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 C,DC,N,OV,Z ...
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... Ws,Wnd 33 FF1R FF1R Ws,Wnd 34 GOTO GOTO Expr GOTO Wn © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set Bit Test then Set Call subroutine ...
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... Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W( Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W( Top-of-Stack (TOS) Push Shadow Registers Go into Sleep or Idle mode Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 C,DC,N,OV,Z 1 ...
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... Wb,#lit5,Wd 64 SWAP SWAP.b Wn SWAP Wn 65 TBLRDH TBLRDH Ws,Wd © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn times Software device Reset Return from interrupt Return with literal in Wn Return from Subroutine ...
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... DS70282B-page 178 Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 2 None 1 2 None ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 20.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24HJ12GP201/202 20.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
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... Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary © 2007 Microchip Technology Inc. ® L security ICs, CAN ® ...
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... Maximum allowable current is a function of device maximum power dissipation (see Table 21-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the V and PGDx pins, which are able to sink/source 12 mA. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 .................................................................................. -0.3V to +5.6V SS ...
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... PIC24HJ12GP201/202 40 35 Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 66 — °C — °C/W 1 63.6 — °C/W 1 80.2 — °C — °C/W 1 © 2007 Microchip Technology Inc. ...
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... Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3 ...
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... OSC1 DD Preliminary 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS 3.3V 35 MIPS . SS © 2007 Microchip Technology Inc. ...
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... Base I current is measured with core off, clock on and all modules turned off. Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to V © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 190
... Preliminary ) PD (3,4) Base Power-Down Current (3) Watchdog Timer Current: ΔI WDT ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 35 MIPS © 2007 Microchip Technology Inc. ...
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... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... DD core voltage DD Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 2mA 3. 2mA 3. -2 -1 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions 2.55 V © 2007 Microchip Technology Inc. ...
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... A Param Symbol Characteristics No. C External Filter Capacitor EFC Value © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
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... OSC2 output Min Typ Max — — 15 — — 50 — — 400 Preliminary ≤ +85°C for Industrial ≤ +125°C for Extended Units Conditions and HS modes when external clock is used to drive OSC1 pF EC mode C™ mode © 2007 Microchip Technology Inc. ...
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... OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Q2 Q3 ...
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... Conditions MHz ECPLL and XTPLL modes MHz ms % Measured over 100 ms period ≤ +85°C for Industrial ≤ +125°C for Extended Conditions ≤ +85° 3.0-3. ≤ +125° 3.0-3. Conditions ≤ +85° 3.0-3. ≤ +125° 3.0-3. © 2007 Microchip Technology Inc. ...
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... INTx Pin High or Low Time (output) INP DI40 T CNx High or Low Time (input) RBP Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
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... TIMER TIMING CHARACTERISTICS V SY12 DD MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 21-1 for load conditions. DS70282B-page 196 SY10 SY20 SY13 Preliminary © 2007 Microchip Technology Inc. SY13 ...
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... Fail-Safe Clock Monitor Delay FSCM Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 T — CY © 2007 Microchip Technology Inc. ...