PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet
PIC16F785-I/SO
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PIC16F785-I/SO Summary of contents
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... Two-Phase Asychronous Feedback PWM, Dual High-Speed Comparators and 2004 Microchip Technology Inc. PIC16F785 Data Sheet 20-Pin Flash-Based 8-Bit CMOS Microcontroller with Dual Operational Amplifiers Preliminary DS41249A ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... kHz, 2.0V, typical - 100 MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical • Timer1 Oscillator Current kHz, 2.0V, typical 2004 Microchip Technology Inc. PIC16F785 Peripheral Features • High-speed Comparator module with: - Two independent analog comparators - Programmable on-chip voltage reference (CV ) module (% of V REF - 1 ...
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... PIC16F785 Program Data Memory Memory Device Flash SRAM EEPROM (words) (bytes) (bytes) PIC16F785 2048 128 Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1 RC4/C2OUT/PH2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- RC7/AN9/OP1+ RB7/SYNC DS41249A-page 2 10-bit A/D Operational I/O Comparators (ch) Amplifiers 256 17 RA0/AN0/C1IN+/ICSPDAT ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. Preliminary PIC16F785 DS41249A-page 3 ...
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... PIC16F785 NOTES: DS41249A-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Data Sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F785 is covered by this Data Sheet Manual available in 20-pin PDIP, SOIC and SSOP packages. Figure 1-1 shows a block diagram of the PIC16F785 device ...
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... PIC16F785 TABLE 1-1: PIC16F785 PINOUT DESCRIPTION Name Pin Function RA0/AN0/C1IN+/ICSPDAT 19 RA1/AN1/C12IN0-/V /ICSPCLK 18 REF RA2/AN2/T0CKI/INT/C1OUT 17 RA3/MCLR RA4/AN3/T1G/OSC2/CLKOUT 3 RA5/T1CKI/OSC1/CLKIN 2 RB4/AN10/OP2- 13 RB5/AN11/OP2+ 12 RB6 11 RB7/SYNC 10 RC0/AN4/C2IN+ 16 RC1/AN5/C12IN1-/PH1 15 RC2/AN6/C12IN2-/OP2 14 RC3/AN7/C12IN3-/OP1 7 DS41249A-page 6 Input Output Type Type RA0 TTL CMOS PORTA I/O w/ prog. pull-up and interrupt-on-change ...
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... TABLE 1-1: PIC16F785 PINOUT DESCRIPTION (CONTINUED) Name Pin Function RC4/C2OUT/PH2 6 RC5/CCP1 5 RC6/AN8/OP1- 8 RC7/AN9/OP1 Legend: TTL = TTL input buffer Schmitt Trigger input buffer Analog Open Drain output High Voltage 2004 Microchip Technology Inc. Input Output Type Type RC4 TTL CMOS PORTC I/O C2OUT — ...
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... PIC16F785 NOTES: DS41249A-page 8 Preliminary 2004 Microchip Technology Inc. ...
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... Program Memory Organization The PIC16F785 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h–07FFh) for the PIC16F785 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
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... PIC16F785 FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F785 File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah ...
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... TABLE 2-2: PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s register 02h PCL Program Counter's (PC) Least Significant Byte 03h ...
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... PIC16F785 TABLE 2-3: PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter's (PC) Least Significant Byte 83h STATUS ...
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... TABLE 2-4: PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module’s register 102h PCL Program Counter's (PC) Least Significant Byte 103h ...
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... PIC16F785 TABLE 2-5: PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 181h OPTION_REG RAPU INTEDG 182h PCL Program Counter's (PC) Least Significant Byte 183h STATUS ...
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... Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-x R/W-x R/W bit 0 (1) ( Bit is unknown DS41249A-page 15 ...
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... Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F785. See Section 15.6 “Watchdog Timer (WDT)” for more information. Legend Readable bit - n = Value at POR DS41249A-page 16 Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘ ...
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... R/W-0 R/W-0 R/W-0 R/W-0 T0IE INTE RAIE T0IF (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 INTF RAIF bit Bit is unknown DS41249A-page 17 ...
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... PIC16F785 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt ...
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... R/W-0 R/W-0 R/W-0 R/W-0 CCP1IF C2IF C1IF OSFIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown DS41249A-page 19 ...
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... PIC16F785 2.2.2.6 PCON Register The Power Control (PCON) register (See Table 15-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register bits are shown in Register 2-6. ...
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... PCLATH Program 2.3.3 STACK The PIC16F785 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit (Status<7>), as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F785 DIRECT ADDRESSING FROM OPCODE RP1 RP0 6 BANK SELECT ...
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... OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz 2004 Microchip Technology Inc. The PIC16F785 can be configured in one of eight clock modes External clock with I/O on RA4 32.768 kHz watch crystal or ceramic resonator oscillator mode Medium gain crystal or ceramic resonator oscillator mode. ...
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... External Clock Modes 3.3.1 OSCILLATOR START-UP TIMER (OST) When the PIC16F785 is configured for any of the crystal oscillator modes (LP HS), the Oscillator Start-up Timer (OST) is enabled, which extends the reset period to allow the oscillator additional time to stabilize. The OST counts 1024 clock periods present ...
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... additional parallel feedback resistor (R may be required for proper ceramic resonator operation (typical value PIC16F785 Sleep To Internal Logic to vary Preliminary PIC16F785 CERAMIC RESONATOR OPERATION ( MODE) OSC1 PIC16F785 Sleep ( OSC2 ( Internal Logic ) may be required for S varies with the oscillator F to ...
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... The user also needs to take into account EXT variation due to tolerance of external RC components used. DS41249A-page 26 3.4 Internal Clock Modes The PIC16F785 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ± ...
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... The HFINTOSC calibration bits are stored in the Calibration Word (CALIB) located in program memory location 2008h. The calibration word is not erased using the specified bulk erase sequence in the PIC16F785 Memory Programming Specification (DS41237) and does not require reprogramming. For more information on the Calibration ...
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... PIC16F785 3.4.3 LFINTOSC The Low-frequency Internal Oscillator (LFINTOSC uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The ...
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... Oscillator Start-up Time and will cause the OSTS bit (OSCCON<3>) to remain clear. 2004 Microchip Technology Inc. When the PIC16F785 is configured for LP, XT modes, the Oscillator Start-up Timer (OST) is enabled (See Section 3.3.1 “Oscillator (OST)”). The OST timer will suspend program execu- tion until 1024 oscillations are counted ...
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... PIC16F785 FIGURE 3-7: TWO-SPEED START- INTOSC T T OST OSC1 0 1 1022 1023 OSC2 Program Counter System Clock 3.7 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator ...
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... The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC16F785 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. ...
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... PIC16F785 REGISTER 3-2: OSCCON — OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh) U-0 R/W-1 — IRCF2 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz ...
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... R/W-x RA5 RA4 RA3 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 INITIALIZING PORTA ;Bank 0 ; ;Init PORTA ;Set RA<2:0> digital I/O ;Bank 1 ;Set RA<3:2> as inputs ; and set RA<5:4,1:0> outputs ;Bank 0 (1) ...
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... TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. Legend Readable bit - n = Value at POR 4.2 Additional Pin Functions Every PORTA pin on the PIC16F785 has an interrupt- on-change option and a weak pull-up option. The next three sections describe these functions. REGISTER 4-3: WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h) U-0 — ...
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... U-0 R/W-0 R/W-0 R/W-0 — IOCA5 IOCA4 IOCA3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 (1) R/W-0 R/W-0 R/W-0 IOCA2 IOCA1 IOCA0 bit Bit is unknown DS41249A-page 35 ...
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... PIC16F785 4.2.3 PORTA PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... Master Clear Reset w/weak pull-up FIGURE 4-4: DATA BUS WPUA RD WPUA TRISA WEAK RD PORTA IOCA IOCA INTERRUPT-ON- I/O PIN CHANGE Preliminary PIC16F785 RA3/MCLR/V PP BLOCK DIAGRAM OF RA3 Q MCLRE WEAK RAPU MCLRE RESET INPUT PIN V SS MCLRE PORTA ...
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... PIC16F785 4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • a TMR1 gate input • a crystal/resonator connection • a clock output FIGURE 4-5: ...
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... IOCA1 BGST VRBB VREN VROE CVROE C1OE C1POL C1SP C1R C1CH1 — — — — T1GSS Preliminary PIC16F785 Value on all Value on: Bit 0 other POR, BOR Resets RA0 --xx xxxx --uu uuuu 0000 0000 0000 0000 RAIF 0000 0000 0000 0000 PS0 1111 1111 ...
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... PIC16F785 4.3 PORTB and TRISB Registers PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 4-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... I • PWM synchronization input and output FIGURE 4-9: I/O PIN PH1EN PH2EN PWM MASTER V SS SYNC OUT DATA BUS PORTB TRISB RD TRISB RD PORTB TO PWM SYNC INPUT Preliminary PIC16F785 BLOCK DIAGRAM OF RB6 I/O PIN BLOCK DIAGRAM OF RB7 I/O PIN DS41249A-page 41 ...
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... PIC16F785 TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 06h, 106h PORTB RB7 RB6 86h, 186h TRISB TRISB7 TRISB6 93h ANSEL1 — — 111h PWMCON0 PRSEN PASEN 11Dh OPA2CON OPAON — Legend unknown unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. ...
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... R/W-1 R/W-1 R/W-1 TRISC5 TRISC4 TRISC3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 INITIALIZING PORTC ;Bank 0 ;Init PORTC ;Bank 1 ;digital I/O ;digital I/O ;Set RC<3:2> as inputs ; and set RC<5:4,1:0> outputs ;Bank 0 ...
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... PIC16F785 4.4.1 PORTC PIN DESCRIPTIONS AND DIAGRAMS Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... The RC4 is configurable to function as one of the following: • a general purpose I/O • a digital output from comparator 2 • a digital output from the Two-Phase PWM FIGURE 4-13: C2OE PH2EN PH2 1 C2OUT 0 DATA BUS PORTC TRISC DD RD TRISC I/O PIN PORTC Preliminary PIC16F785 BLOCK DIAGRAM OF RC4 I/O PIN DS41249A-page 45 ...
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... PIC16F785 4.4.1.8 RC5/CCP1 The RC5 is configurable to function as one of the following: • a general purpose I/O • a digital input for the capture/compare • a digital output for the CCP TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h, 107h PORTC RC7 ...
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... The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut-off during Sleep. 8-bit Prescaler PSA 8 (1) (1) PS<0:2> 16-bit 16 PSA (2) WDTPS<3:0> Preliminary PIC16F785 ® Mid-Range Reference Data Bus 8 1 SYNC 2 TMR0 Cycles 0 Set Flag bit T0IF on Overflow (1) 1 WDT ...
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... PIC16F785 5.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... TIMER1 MODULE WITH GATE CONTROL The Timer1 module is the 16 bit counter of the PIC16F785. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • ...
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... PIC16F785 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit Timer with prescaler • 16-bit Synchronous counter • 16-bit Asynchronous counter In Timer mode, Timer1 is incremented on every instruc- tion cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In ...
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... R = Readable bit - n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) (2) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS41249A-page 51 ...
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... PIC16F785 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor ...
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... TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W-0 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 /4) has a prescale option OSC ) h R/W-0 R/W-0 R/W-0 bit Bit is unknown DS41249A-page 53 ...
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... PIC16F785 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: ...
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... U-0 R/W-0 R/W-0 R/W-0 — DC1B1 DC1B0 CCP1M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 CCP MODE - TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 ...
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... PIC16F785 8.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC5/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge When a capture is made, the interrupt request flag bit CCP1IF (PIR1< ...
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... TMR1CS — — — — DC1B0 CCP1M3 CCP1M2 CCP1M1 TRISC4 TRISC3 TRISC2 C2IE C1IE OSFIE TMR2IE Preliminary PIC16F785 Value on Value on: Bit 1 Bit 0 all other POR, BOR Resets INTF RAIF 0000 0000 0000 0000 TMR2IF TMR1IF 0000 0000 0000 0000 xxxx xxxx ...
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... PIC16F785 8.3 CCP PWM Mode In Pulse Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the RC5/CCP1 pin. Since the RC5/CCP1 pin is multiplexed with the PORTC data latch, the TRISC<5> must be cleared to make the RC5/CCP1 pin an output. Note: ...
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... Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 6. Enable PWM output after a new PWM cycle has started: • Wait until TMR2 overflows (TMR2IF bit is set). • Enable the RC5/CCP1 pin output by clearing the TRISC<5> bit. Preliminary PIC16F785 log 4 PR2 + 1 ----------------------------------------- bits = log 2 ...
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... PIC16F785 TABLE 8-4: REGISTERS ASSOCIATED WITH CCP AND TIMER2 Addr Name Bit 7 Bit 6 Bit 5 0Bh, INTCON GIE PEIE 8Bh 0Ch PIR1 EEIF ADIF CCP1IF 11h TMR2 Timer2 Module register 12h T2CON — TOUTPS3 TOUTPS2 13h CCPR1L Capture/Compare/PWM Register1 Low Byte 14h ...
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... C1SP (CM1CON0<3>) configures the speed of the comparator. When C1SP is set, the comparator oper- ates at its normal speed. Clearing C1SP operates the comparator in a slower, low-power mode. out- REF on the Preliminary PIC16F785 C1OUTPUT STATE VERSUS INPUT CONDITIONS C1POL C1OUT ...
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... PIC16F785 FIGURE 9-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> RA1/AN1/C12IN0-/V /ICSPCLK REF RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 C1R RA0/AN0/C1IN+/ICSPDAT C1V REF Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. DS41249A-page MUX 2 Q3*RD_CM1CON0 3 (1) C1ON C1SP ...
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... Microchip Technology Inc. R-0 R/W-0 R/W-0 R/W-0 C1OE C1POL C1SP output REF REF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 R/W-0 C1R C1CH1 C1CH0 bit 0 (1) /ICSPCLK x = Bit is unknown DS41249A-page 63 ...
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... PIC16F785 9.1.2 COMPARATOR C2 CONTROL REGISTERS The CM2CON0 register is a functional copy of the CM1CON0 register described in Section 9.1.1. A sec- ond control register, CM2CON1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs. 9.1.2.1 Control Register CM2CON0 The CM2CON0 register, shown in Register 9-2, con- tains the control and Status bits for Comparator C2. Setting C2ON (CM2CON0< ...
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... Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 C2OE C2POL C2SP (1) REF /ICSPCLK REF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 C2R C2CH1 C2CH0 bit Bit is unknown DS41249A-page 65 ...
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... PIC16F785 9.1.2.2 Control Register CM2CON1 Comparator C2 has one additional feature: its output can be synchronized to the Timer1 clock input. Setting C2SYNC (CM2CON1<0>) synchronizes the output of Comparator 2 to the falling edge of Timer 1’s clock input (see Figure 9-2 and Register 9-3). REGISTER 9-3: ...
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... CxIF bits will still be set if an interrupt condition occurs. The comparator interrupt of the PIC16F785 differs from previous designs in that the interrupt flag is set by the mismatch edge and not the mismatch level. This ...
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... PIC16F785 NOTES: DS41249A-page 68 Preliminary 2004 Microchip Technology Inc. ...
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... VOLTAGE REFERENCES There are two voltage references available in the PIC16F785: The voltage referred to as the comparator reference ( variable voltage based on V REF The voltage referred to as the VR reference (VR fixed voltage derived from a stable bandgap source. Each source may be individually routed internally to the ...
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... PIC16F785 REGISTER 10-1: VOLTAGE REFERENCE CONTROL REGISTER (VRCON: 99H) R/W-0 R/W-0 C1VREN C2VREN bit 7 bit 7: C1VREN: Comparator 1 Voltage Reference Enable bit circuit powered on and routed to C1V REF 0 = 1.2 Volt VR routed to C1V bit 6: C2VREN: Comparator 2 Voltage Reference Enable bit circuit powered on and routed to C2V REF ...
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... VR analog reference REF /ICSPCLK pin is CV REF /ICSPCLK pin is controlled by VROE REF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ - bit as set ‘0’ = bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 U-0 VROE CVROE — bit0 voltage REF x = bit is unknown ...
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... PIC16F785 10.2.1 VR STABILIZATION PERIOD When the voltage reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See the electrical specifications section for the minimum delay requirement ...
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... When OPA1 or OPA2 is enabled, the RC3/AN7/C12IN3-/OP1 pin, or RC2/AN6/C12IN2-/OP2 pin respectively, is driven by the op amp output, not by the PORTC driver. Refer to the Electrical specifications for the op amp output drive capability. OPA1CON<OPAON> OPA1 TO ADC and Comparator MUXs OPA2CON<OPAON> OPA2 TO ADC and Comparator MUXs Preliminary PIC16F785 DS41249A-page 73 ...
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... PIC16F785 REGISTER 11-1: OP AMP 1 CONTROL REGISTER (OPA1CON: 11Ch) R/W-0 OPAON bit 7 bit 7 OPAON: Op Amp Enable bit Amp1 is enabled Amp1 is disabled bit 6-0 Unimplemented: Read as ‘0’ Legend Readable bit - n = Value at POR REGISTER 11-2: OP AMP 2 CONTROL REGISTER (OPA2CON: 11Dh) R/W-0 OPAON bit 7 ...
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... ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 — — — Preliminary PIC16F785 Value on Value on: Bit 0 all other POR, BOR RESETS — 0--- ---- 0--- ---- — 0--- ---- 0--- ---- — 1111 ---- 1111 ---- 1111 1111 DS41249A-page 75 ...
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... PIC16F785 NOTES: DS41249A-page 76 Preliminary 2004 Microchip Technology Inc. ...
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... CONVERTER (A/D) MODULE The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representa- tion of that signal. The PIC16F785 has twelve analog I/O inputs, plus two internal inputs, multiplexed into one sample and hold circuit. The output of the sample and ...
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... Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 12.1.2 CHANNEL SELECTION There are fourteen analog channels on the PIC16F785. The CHS<3:0> bits (ADCON0<5:2>) control which channel is connected to the sample and hold circuit. TABLE 12- ...
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... ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input ADRESH bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 Preliminary PIC16F785 sample. Instead, the ADRESL LSB bit 0 Unimplemented: Read as ‘0’ LSB bit 0 10-bit A/D Result ...
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... PIC16F785 REGISTER 12-1: ANSEL0 — ANALOG SELECT REGISTER (ADDRESS: 91h) R/W-1 R/W-1 ANS7 ANS6 bit 7 bit 7-0: ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively Analog input. Pin is assigned as analog input Digital I/O. Pin is assigned to port or special function. ...
Page 83
... Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 U-0 ADCS1 ADCS0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown U-0 U-0 U-0 — — — ...
Page 84
... PIC16F785 12.1.7 CONFIGURING THE A/D After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 18.0 “Electri- cal Specifications” ...
Page 85
... 10k ln(0.0004885) 50°C- 25°C 0.05µ /° has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD Preliminary PIC16F785 , see ACQ ® Mid-Range Reference Manual + Temperature Coefficient charged to within 1/2 lsb charge response to V APPLIED DS41249A-page 83 ...
Page 86
... PIC16F785 FIGURE 12-4: ANALOG INPUT MODEL ANx PIN Legend C = Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD DS41249A-page Sampling Switch LEAKAGE V = 0.6V T ± 500 Preliminary C HOLD ...
Page 87
... When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted and the A/D module is turned off. The ADON bit remains set. Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal V Zero-Scale REF Transition Preliminary PIC16F785 DS41249A-page 85 ...
Page 88
... PIC16F785 12.4 Effects of Reset A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL regis- ters are unchanged. 12.5 Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” ...
Page 89
... The PWM Counter will be reset and held at zero when both PH1EN and PH2EN (PWMCON0<1:0>) are false. If the PWM is configured as a slave, the PWM Counter will remain reset at zero until the first SYNC input is received. Preliminary PIC16F785 PHASE RESOLUTION 360 ------------------------- = DEG PER ...
Page 90
... PIC16F785 13.5 Active PWM Output Level The PWM output signal can be made active high or low by setting or resetting the corresponding POL bit (see Register 13-3 and Register 13-4). When POL is ‘1’ the active output state When POL is ‘0’ the OL active output state is V ...
Page 91
... BLANK2 BLANK1 SYNC1 SYNC0 clock period after it is set OSC clock period after it is set OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 PH2EN PH1EN bit bit is unknown DS41249A-page 89 ...
Page 92
... PIC16F785 REGISTER 13-2: PWM CLOCK CONTROL REGISTER (PWMCLK: 112h) R/W-0 R/W-0 PWMASE PWMP1 bit 7 bit 7 PWMASE: PWM Auto-Shutdown event Status bit 0 = PWM outputs are operating shutdown event has occured. PWM outputs are inactive. bit 6-5 PWMP<1:0>: PWM Clock Prescaler bits 00 = PWM Clock = F ...
Page 93
... R = Readable bit -n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 C1EN PH4 PH3 PH2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 PH1 PH0 bit bit is unknown DS41249A-page 91 ...
Page 94
... PIC16F785 REGISTER 13-4: PWM PHASE 2 CONTROL REGISTER (PWMPH2: 114h) R/W-0 R/W-0 POL C2EN bit 7 bit 7 POL: PH2 Output Polarity bit 1 = PH2 Pin is active low 0 = PH2 Pin is active high bit 6 C2EN: Comparator 2 Enable bit 1 = PH2 is reset when C2OUT is high 0 = PH2 ignores Comparator 2 ...
Page 95
... Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0 pha1 SHUTDOWN pwm_clk 0 1 pwm_count 2 Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2 FIGURE 13-6: 2 PHASE PWM START UP TIMING F OSC PWMP<1:0> 01, PER<4:0> pwm_clk pwm_count SYNC PHnEN pwm_clk pwm_count PHnEN 2004 Microchip Technology Inc Preliminary PIC16F785 DS41249A-page 93 ...
Page 96
... PWM drive pulses into Q1. If the output voltage is too high, then the voltage to the non-inverting input of comparator 1 will fall, resulting in shorter PWM drive pulses into Q1. PIC16F785 F OSC FET DRIVER PH1 ...
Page 97
... OVRLP bit of the PWM control register (PWMCON1<7>). R/W-0 R/W-0 R/W-0 R/W-0 CMDLY4 CMDLY3 CMDLY2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘0’ = bit is cleared Preliminary PIC16F785 R/W-0 R/W-0 CMDLY1 CMDLY0 bit bit is unknown DS41249A-page 95 ...
Page 98
... PIC16F785 FIGURE 13-8: COMPLEMENTARY OUTPUT PWM BLOCK DIAGRAM PS<1:0> F OSC PRESCALE PWMASE PWMPH1<4:0> PWMPH2<4:0> PWMPH1<C1EN> C1OUT PWMPH1<C2EN> C2OUT COMOD<1:0> SHUTDOWN FIGURE 13-9: COMPLEMENTARY OUTPUT PWM TIMING F OSC PWMP<1:0> 01, PER<4:0> pwm_clk pwm_count SYNC C1OUT Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0, COMOD<1:0> = 0x01 ...
Page 99
... PH2EN PWMP0 PER4 PER3 PER2 PER1 C1EN PH4 PH3 PH2 PH1 C1EN PH4 PH3 PH2 PH1 Preliminary PIC16F785 Value on all Value on: Bit 0 other POR, BOR Resets — --00 000- --00 000- VR0 000- 0000 000- 0000 C1CH0 0000 0000 0000 0000 C2CH0 0000 0000 ...
Page 100
... PIC16F785 NOTES: DS41249A-page 98 Preliminary 2004 Microchip Technology Inc. ...
Page 101
... EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. The PIC16F785 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 14-1: EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
Page 102
... PIC16F785 14.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non- implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software ...
Page 103
... EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: • brown-out • power glitch • software malfunction Preliminary PIC16F785 ;EEDAT not changed ; from previous write ;YES, Read the ; value written ;Is data the same ;No, handle error ...
Page 104
... PIC16F785 14.6 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 15-1) to ‘0’. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM recommended to code-protect the program memory when code-protecting data memory ...
Page 105
... SPECIAL FEATURES OF THE CPU The PIC16F785 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...
Page 106
... PIC16F785 REGISTER 15-1: CONFIG — CONFIGURATION WORD (ADDRESS: 2007h) — — FCMEN IESO BOREN1 BOREN0 bit 13 bit 13-12 Unimplemented: Read as ‘1’ bit 11 FCMEN: Fail Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 10 IESO: Internal External Switchover bit ...
Page 107
... Reset The PIC16F785 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...
Page 108
... For additional information, refer to the “Power-up Trouble Shooting” Application Note (DS00607). 15.3.2 MASTER CLEAR (MCLR) PIC16F785 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
Page 109
... BOR 64 ms Reset. 15.3.5 BOR CALIBRATION The PIC16F785 stores the BOR calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the speci- fied bulk erase sequence in the PIC16F785 Memory Programming Specification (DS41237) and thus, does not require reprogramming ...
Page 110
... Then bringing MCLR high will begin execution immediately (see Figure 15-5). This is useful for testing purposes or to synchronize more than one PIC16F785 device operating in parallel. Table 15-5 shows the Reset conditions for some special registers, while Table 15-4 shows the Reset conditions for all the registers ...
Page 111
... PWRT Time Out OST Time Out Internal Reset FIGURE 15-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time Out OST Time Out Internal Reset 2004 Microchip Technology Inc. T PWRT T OST T PWRT T OST DD T PWRT T OST Preliminary PIC16F785 ) DS41249A-page 109 ...
Page 112
... PIC16F785 TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS Power-on Register Address Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx PORTA 05h --x0 x000 PORTB 06h xx00 ---- ...
Page 113
... Preliminary PIC16F785 ---- uuuu --uu uuuu --uu uuuu --uu uuu- uuu- uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- ---- uuuu uuuu -uuu ---- uuuu uuuu uuuu uuuu ...
Page 114
... PIC16F785 TABLE 15-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Legend unchanged unknown, — = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1 ...
Page 115
... Interrupts The PIC16F785 has 11 sources of interrupt: • External Interrupt RA2/INT • TMR0 Overflow Interrupt • PORTA Change Interrupt • 2 Comparator Interrupts • A/D Interrupt • Timer 1 Overflow Interrupt • Timer 2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • ...
Page 116
... PIC16F785 15.4.1 RA2/AN2/T0CKI/INT/C1OUT INTERRUPT External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin is edge-triggered; either rising, if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RA2/AN2/T0CKI/ INT/C1OUT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in soft- ware in the Interrupt Service Routine before re- enabling this interrupt ...
Page 117
... T0IE INTE RAIE T0IF INTF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000 Preliminary PIC16F785 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle , where T = instruction cycle time. ...
Page 118
... Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F785 normally does not require saving the PCLATH. However, if com- puted GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR ...
Page 119
... Watchdog Timer (WDT) For PIC16F785, the WDT has been modified from previous PIC16F devices. The new WDT is code and functionally compatible with previous PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to scale the value for the WDT and TMR0 at the same time ...
Page 120
... PIC16F785 REGISTER 15-2: WDTCON — WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h) U-0 — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) ...
Page 121
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. Preliminary PIC16F785 DS41249A-page 119 ...
Page 122
... PIC16F785 FIGURE 15-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst( Inst(PC) = Sleep Fetched Instruction Sleep Inst( Executed Note 1: XT Oscillator mode assumed 1024T (drawing not to scale). This delay does not apply to EC, RC and INTOSC Oscillator modes. ...
Page 123
... ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off by performing a bulk erase. See the PIC16F785 Memory Programming Specification (DS41237) for more information. 15.9 ID Locations Four memory locations (2000h – 2003h) are desig- nated as ID locations where the user can store check- sum or other code identification numbers ...
Page 124
... On the bottom of the header is a 20-pin socket that plugs into the user’s target via the 20-pin stand-off connector. When the ICD pin on the PIC16F785 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...
Page 125
... INSTRUCTION SET SUMMARY The PIC16F785 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
Page 126
... PIC16F785 TABLE 16-2: PIC16F785 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS f, d Add W and f ADDWF f, d AND W with f ANDWF f Clear f CLRF - Clear W CLRW f, d Complement f COMF f, d Decrement f DECF f, d Decrement f, Skip if 0 DECFSZ f, d Increment f INCF f, d Increment f, Skip if 0 ...
Page 127
... None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruc- tion is discarded and a NOP is executed instead, making this a 2-cycle instruction. Preliminary PIC16F785 f,b 127 7 f,b 127 7 7 127 ...
Page 128
... PIC16F785 CALL Call Subroutine Syntax: [ label ] CALL k Operands 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) Status Affected: None Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immedi- ate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH ...
Page 129
... W register. If ‘d’ the destination is file register ‘f’ itself. ‘d’ useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example MOVF After Instruction Preliminary PIC16F785 IORLW k 255 (W) IORWF f,d 127 (destination) MOVF f,d 127 1000 dfff ffff ...
Page 130
... PIC16F785 MOVLW Move Literal to W Syntax: [ label ] MOVLW k Operands 255 Operation: k (W) Status Affected: None Encoding: 11 00xx Description: The eight bit literal ‘k’ is loaded into W register. The don’t cares will assemble as 0’s Words: 1 Cycles: 1 Example MOVLW 0x5A After Instruction ...
Page 131
... This is a two-cycle instruction. 2004 Microchip Technology Inc. RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example Preliminary PIC16F785 Rotate Left f through Carry [ label ] RLF f 127 d [0,1] See description below C 00 1101 dfff ffff The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘ ...
Page 132
... PIC16F785 RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Encoding: 00 1100 Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ the result is placed in the W register. If ‘ ...
Page 133
... Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Preliminary PIC16F785 Swap Nibbles label ] SWAPF f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None 00 1110 dfff ffff The upper and lower nibbles of register ‘ ...
Page 134
... PIC16F785 XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands 255 Operation: (W) .XOR. k Status Affected: Z Encoding: 11 1010 Description: The contents of the W register are XOR’ed with the eight bit literal ‘k’. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW 0xAF ...
Page 135
... The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Preliminary PIC16F785 ® ® standard HEX DS41249A-page 133 ...
Page 136
... PIC16F785 17.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 137
... MPLAB PM3 connects to the host PC via an RS- 232 or USB cable. MPLAB PM3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an SD/MMC card for file storage and secure data appli- cations. Preliminary PIC16F785 development tool, TM (ICSP TM ) ...
Page 138
... PIC16F785 17.14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...
Page 139
... PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. ® IDE software, Preliminary PIC16F785 TM development DS41249A-page 137 ...
Page 140
... PIC16F785 NOTES: DS41249A-page 138 Preliminary 2004 Microchip Technology Inc. ...
Page 141
... Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to V 2004 Microchip Technology Inc. ........................................................................... -0. – ∑ DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up Preliminary PIC16F785 + 0.3V ∑ {( ∑(V – DS41249A-page 139 ...
Page 142
... PIC16F785 FIGURE 18-1: PIC16F785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note: The shaded region indicates the permissible combinations of voltage and frequency. DS41249A-page 140 Frequency (MHz) Preliminary 20 2004 Microchip Technology Inc. ...
Page 143
... DC Characteristics: PIC16F785 -I (Industrial), PIC16F785 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001A D001B D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V voltage above which POR DD the internal POR releases D003A V V voltage below which PARM DD the internal POR rearms ...
Page 144
... PIC16F785 18.2 DC Characteristics: PIC16F785-I (Industrial) DC Characteristics Param Device Characteristics No. D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 D018 Legend: TBD = To Be Determined. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 145
... DC Characteristics: PIC16F785-I (Industrial) DC Characteristics Param Device Characteristics No. D020 Power-down Base Current ( D021 D022 D023 D023A D024 D024A D025 D026 D027 D028 Legend: TBD = To Be Determined. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 146
... PIC16F785 18.3 DC Characteristics: PIC16F785-E (Extended) DC Characteristics Param Device Characteristics No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E D018E Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 147
... DC Characteristics: PIC16F785-E (Extended) DC Characteristics Param Device Characteristics No. D020E Power-down Base Current ( D021E D022E D023E D023E D024E D024E D025E D026E D027E D028E Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 148
... PIC16F785 18.4 DC Characteristics: PIC16F785 -I (Industrial), PIC16F785 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) (1) D033A OSC1 (HS mode) Input High Voltage V I/O ports ...
Page 149
... DC Characteristics: PIC16F785 -I (Industrial), PIC16F785 -E (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. Capacitive Loading Specs on Output Pins D100 COSC OSC2 pin 2 D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write DRW DD D122 T Erase/Write cycle time ...
Page 150
... PIC16F785 18.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
Page 151
... All specified values Preliminary PIC16F785 Conditions LP mode (complementary input only) LP Osc mode µs LP mode (complementary input only Osc mode ns EC Osc mode ns XT Osc mode µ ...
Page 152
... PIC16F785 TABLE 18-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Param Sym Characteristic No. F10 F Internal Calibrated OSC INTOSC Frequency F14 T Oscillator wake-up from IOSC Sleep start-up time These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 153
... Time-out Internal Reset Watchdog Timer Reset I/O Pins 2004 Microchip Technology Inc. Min Typ† Max — 50 150 * — — 300 100 — 0 — — 10 — — T — OSC Preliminary PIC16F785 Units Conditions ns ns — ns — — ns — DS41249A-page 151 ...
Page 154
... PIC16F785 FIGURE 18-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR) Note delay only if PWRTE bit in Configuration Word is programmed to ‘0’. TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Param Sym Characteristic No ...
Page 155
... CY With Prescaler No Prescaler 0 With Prescaler Greater of Synchronous, No Prescaler 0 Synchronous, with Prescaler Asynchronous Synchronous, No Prescaler 0 Synchronous, with Prescaler Asynchronous Synchronous Greater of Asynchronous Preliminary PIC16F785 49 Typ† Max Units Conditions + 20 — — — — — — — — ns — — prescale + 40 value ( ..., 256 — ...
Page 156
... PIC16F785 FIGURE 18-8: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP1 (Capture mode) CCP1 (Compare or PWM mode) Note: Refer to Figure 18-2 for load conditions. TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Param Symbol Characteristic No. 50* TccL CCP1 input low time 51* TccH CCP1 input high time 52* TccP CCP1 input period ...
Page 157
... Standard Operating Conditions (unless otherwise stated) Operating temperature Min Typ Max TBD 1.200 TBD — 150 TBD — 200 — 10 100* Preliminary PIC16F785 -40°C T +125°C A Max Units Comments 5 mV – 1.5 V 200* nA — dB 20* ns Internal 40* ns Output to pin -40° ...
Page 158
... PIC16F785 TABLE 18-10: OPERATIONAL AMPLIFIER (OPA) DC SPECIFICATIONS OPA DC Characteristics Param Symbol Characteristics No. OPA01* V Input Offset Voltage OS Input current and impedance OPA02* I Input bias current B OPA03* I Input offset bias current OS Common Mode OPA04* V Common mode input range CM OPA05* CMR Common mode rejection ...
Page 159
... TABLE 18-12: PIC16F785 A/D CONVERTER CHARACTERISTICS: Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute ABS (1) Error* A03 E Integral Error IL A04 E Differential Error DL A05 E Full Scale Range FS A06 E Offset Error OFF A07 E Gain Error GN A10 — Monotonicity A20 V Reference Voltage REF A20A ...
Page 160
... OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T allows the SLEEP instruction to be executed. TABLE 18-13: PIC16F785 A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. 130 T A/D Clock Period AD 130 T A/D Internal RC ...
Page 161
... A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T allows the SLEEP instruction to be executed. TABLE 18-14: PIC16F785 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param Sym Characteristic No. 130 T A/D Internal RC AD Oscillator Period ...
Page 162
... PIC16F785 NOTES: DS41249A-page 160 Preliminary 2004 Microchip Technology Inc. ...
Page 163
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. Example PIC16F785 -I/P 0415017 Example PIC16F785 -E/SO 0415017 Example PIC16F785 -I/SS 0415017 Preliminary PIC16F785 DS41249A-page 161 ...
Page 164
... PIC16F785 19.2 Package Details The following sections give the technical details of the packages. 20-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...
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... L .016 .033 .050 .009 .011 .013 B .014 .017 .020 Preliminary PIC16F785 ) A2 MILLIMETERS MIN NOM MAX 20 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 12.60 12.80 13.00 0.25 0.50 ...
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... PIC16F785 20-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions ...
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... This is a new data sheet. 2004 Microchip Technology Inc. APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from the PIC16F684 PICmicro device to the PIC16F785. B.1 PIC16F684 to PIC16F785 TABLE B-1: FEATURE COMPARISON Feature Max Operating Speed Max Program ...
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... PIC16F785 NOTES: DS41249A-page 166 Preliminary 2004 Microchip Technology Inc. ...
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... CCPR1L Register ............................................................... 55 Clock Sources..................................................................... 23 CM1CON0 .......................................................................... 63 CM2CON1 .......................................................................... 66 Code Examples Assigning Prescaler to Timer0.................................... 48 Assigning Prescaler to WDT....................................... 48 Changing Between Capture Prescalers ..................... 56 Data EEPROM Read................................................ 101 Data EEPROM Write ................................................ 101 EEPROM Write Verify .............................................. 101 Indirect Addressing..................................................... 22 Initializing A/D............................................................. 82 Initializing PORTA ...................................................... 33 Initializing PORTB ...................................................... 40 Preliminary PIC16F785 DS41249A-page 167 ...
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... PIC16F785 Initializing PORTC....................................................... 43 Interrupt Context Saving ........................................... 116 Code Protection ................................................................ 121 Comparator Module ............................................................ 61 Associated registers.................................................... 72 C1 Output State Versus Input Conditions ................... 61 C2 Output State Versus Input Conditions ................... 64 Comparator Interrupts ................................................. 67 Effects of a RESET ..................................................... 67 Comparator Voltage Reference (CV ) REF Specifications ............................................................ 155 Comparators C2OUT as T1 Gate ..................................................... 50 Specifications ...
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... CCP1CON (CCP Operation) ...................................... 55 CCPR1H..................................................................... 55 CCPR1L ..................................................................... 55 CM1CON0 (C1 Control) ............................................. 63 CM1CON0 (C2 Control) CM2CON0 .......................................................... 65 CM2CON1 (C2 control) .............................................. 66 CONFIG (Configuration Word) ................................. 104 Data Memory Map ...................................................... 10 EEADR (EEPROM Address) ...................................... 99 EECON1 (EEPROM Control 1) ................................ 100 EECON2 (EEPROM Control 2) ................................ 100 EEDAT (EEPROM Data) ............................................ 99 INTCON (Interrupt Control) ........................................ 17 IOCA (Interrupt-on-change PORTA) .......................... 35 Preliminary PIC16F785 DS41249A-page 169 ...
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... PIC16F785 OPAMP Control Register (OPACON) ......................... 74 OPTION_REG (Option) .............................................. 16 OSCCON (Oscillator Control) ..................................... 32 PCON (Power Control) ............................................. 108 PIE1 (Peripheral Interrupt Enable 1) ........................... 18 PIR1 (Peripheral Interrupt Register 1) ........................ 19 PORTA........................................................................ 33 PORTB........................................................................ 40 PORTC ....................................................................... 43 PWMCLK (PWM clock control) ................................... 90 PWMCON0 (PWM control 0) ...................................... 89 PWMCON1 (PWM control 1) ...................................... 95 PWMPH1 (PWM Phase 1 control) .............................. 91 PWMPH2 (PWM Phase 2 control) ...
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... Watchdog Timer (WDT) .................................................... 117 Associated registers.................................................. 118 Clock Source............................................................. 117 Modes ....................................................................... 117 Period........................................................................ 117 Specifications............................................................ 152 WDTCON Register ........................................................... 118 WPUA (weak pullup) ........................................................... 34 WPUA Register ................................................................... 34 WWW, On-Line Support ....................................................... 3 X XORLW Instruction ........................................................... 132 XORWF Instruction ........................................................... 132 2004 Microchip Technology Inc. Preliminary PIC16F785 DS41249A-page 171 ...
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... PIC16F785 NOTES: DS41249A-page 172 Preliminary 2004 Microchip Technology Inc. ...
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... PIC16F785 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape Internet Explorer ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? 2004 Microchip Technology Inc. Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41249A Preliminary PIC16F785 DS41249A-page 174 ...
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... Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. XXX Examples: Pattern a) PIC16F785 – E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC16F785 – I/SO = Industrial Temp., SOIC package, 20 MHz Preliminary PIC16F785 ...
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... Fax: 33-1-69-30-90-79 Germany D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 08/16/04 2004 Microchip Technology Inc. ...