PIC12F675-I/MF Microchip Technology, PIC12F675-I/MF Datasheet - Page 42
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PIC12F675-I/MF
Manufacturer Part Number
PIC12F675-I/MF
Description
IC MCU CMOS 1K FLASH W/AD 8-DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
4.PIC12F675-IMD.pdf
(128 pages)
Specifications of PIC12F675-I/MF
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
128Byte
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 53270-913
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F675-I/MF
Manufacturer:
MICROCHIP
Quantity:
875
Part Number:
PIC12F675-I/MF
Manufacturer:
MICROCHI
Quantity:
20 000
PIC12F629/675
REGISTER 6-2:
6.9
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a '1' to this register, a
simulated interrupt may be initiated.
The
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
TABLE 6-2:
DS41190E-page 40
0Bh/8Bh
0Ch
19h
8Ch
85h
99h
Legend:
Address
CMIE
Comparator Interrupts
bit 7
bit 6
bit 5
bit 4
bit 3-0
INTCON
PIR1
CMCON
PIE1
TRISIO
VRCON
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
bit
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
(PIE1<3>)
VREN
VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
EEIE
Bit 7
EEIF
bit 7
VREN: CV
1 = CV
0 = CV
Unimplemented: Read as '0'
VRR: CV
1 = Low range
0 = High range
Unimplemented: Read as '0'
VR3:VR0: CV
When VRR = 1: CV
When VRR = 0: CV
GIE
Legend:
R = Readable bit
- n = Value at POR
—
—
R/W-0
VREN
REF
REF
COUT
ADIE
Bit 6
PEIE
ADIF
and
REF
—
—
REF
circuit powered on
circuit powered down, no I
Range Selection bit
REF
Enable bit
U-0
the
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
—
Bit 5
T0IE
VRR
value selection 0 ≤ VR [3:0] ≤ 15
—
—
—
REF
REF
PEIE
= (VR3:VR0 / 24) * V
= V
R/W-0
INTE
CINV
Bit 4
VRR
DD
—
—
—
W = Writable bit
’1’ = Bit is set
bit
/4 + (VR3:VR0 / 32) * V
CMIE
GPIE
CMIF
Bit 3
VR3
CIS
DD
R/W-0
—
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
drain
Note:
Bit 2
CM2
T0IF
VR2
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
DD
—
—
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
VR3
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
Bit 1
INTF
CM1
VR1
DD
—
—
TMR1IE
TMR1IF
R/W-0
GPIF
Bit 0
CM0
VR0
VR2
© 2007 Microchip Technology Inc.
0000 0000
00-- 0--0
-0-0 0000
00-- 0--0
--11 1111
0-0- 0000
POR, BOD
Value on
x = Bit is unknown
R/W-0
VR1
0000 000u
00-- 0--0
-0-0 0000
00-- 0--0
--11 1111
0-0- 0000
Value on
RESETS
all other
R/W-0
VR0
bit 0