PIC12F519-I/P Microchip Technology, PIC12F519-I/P Datasheet - Page 46

• Manufacturer Part Number: PIC12F519-I/P
• Description: IC PIC MCU FLASH 1KX12 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F519-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.5KB (1K x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• Package: 8PDIP
• Device Core: PIC
• Family Name: PIC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162096 - HEADER MPLAB ICD2 PIC16F526 8/14AC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F519
8.5
On the PIC12F519 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the devices in
a Reset condition after MCLR has reached a logic high
(V
MCLR and using an external RC network connected to
the MCLR input is not required in most cases. This
allows savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the
RB3/MCLR/V
The Device Reset Time delays will vary from
chip-to-chip due to V
ation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 8-5:
DS41319A-page 44
INTOSC, EXTRC
LP, XT
IH
Configuration
Oscillator
MCLR) level. Programming RB3/MCLR/V
Device Reset Timer (DRT)
PP
pin as a general purpose input.
DRT (DEVICE RESET TIMER
PERIOD)
DD
18 ms (typical)
1 ms (typical)
POR Reset
, temperature and process vari-
DD
to rise above V
18 ms (typical)
10 μs (typical)
Subsequent
DD
Resets
min. and
PP
Preliminary
as
8.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (RB5)/OSC1/CLKIN pin
and the internal 4 or 8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 8.1
“Configuration Bits”). Refer to the PIC12F519 Pro-
gramming Specifications to determine how to access
the Configuration Word.
8.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These peri-
ods vary with temperature, V
cess variations (see DC specs).
Under worst-case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Watchdog Timer (WDT)
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
© 2007 Microchip Technology Inc.
DD
DD
and part-to-part pro-
= Min., Temperature