DS89C430-QNL+ Maxim Integrated Products, DS89C430-QNL+ Datasheet - Page 35

• Manufacturer Part Number: DS89C430-QNL+
• Description: IC MCU FLASH 16KB 33MHZ 44-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C430-QNL+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC, 44-PLCC
• Processor Series: 89C
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 33MHz
• No. Of Timers: 3
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Interface Type: UART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 13. Page Mode 1, External Data Memory Access
(PAGES = 01, Stretch = 4, CD = 10)
Interrupts
The DS89C430 provides 13 interrupt sources. All interrupts, with the exception of the power fail, are controlled by a
series combination of individual enable bits and a global enable (EA) in the interrupt-enable register (IE.7). Setting
EA to a logic 1 allows individual interrupts to be enabled. Setting EA to a logic 0 disables all interrupts regardless of
the individual interrupt-enable settings. The power-fail interrupt is controlled by its individual enable only.
The interrupt enables and priorities are functionally identical to those of the 80C52, except that the DS89C430
supports five levels of interrupt priorities instead of the original two.
RD/WR
Port 0
Port 2
Port 0
Port 2
RD/WR
XTAL1
PSEN
PSEN
ALE
ALE
LSB LSB
LSB
Inst Inst
Inst Inst Inst Inst
Instruction
Instruction
LSB
MOVX
MOVX
Fetch
Fetch
LSB
LSB
Inst
Cycle
Cycle
LSB
LSB
1st
1st
Inst
Cycle
2nd
Cycle
2nd
MSB
Cycle
3rd
Cycle
3rd
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
MOVX Instruction (Page miss)
MOVX Instruction (Page hit)
35 of 46
Memory Access (Stretch = 4)
Memory Access (Stretch = 4)
Cycle
4th
Cycle
4th
Cycle
5th
Cycle
Data
LSB
9th
Data
LSB
Cycle
9th
LSB LSB LSB
Inst Inst Inst
LSB LSB
Inst
Inst