MAXQ7667AACM/V+ Maxim Integrated Products, MAXQ7667AACM/V+ Datasheet - Page 23

• Manufacturer Part Number: MAXQ7667AACM/V+
• Description: IC MCU-BASED DAS 16BIT 48-LQFP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7667AACM/V+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 2.75 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: MAXQ7667
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: UART, JTAG, LIN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MAXQ7667EVKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The joint test action group (JTAG) IEEE 1149.1 standard
defines a unique method for in-circuit testing and pro-
gramming. The MAXQ7667 conforms to this standard,
implementing an external test access port (TAP) and
internal TAP controller for communication with a JTAG
bus master, such as an automatic test equipment (ATE)
system. The MAXQ7667 JTAG interface does not allow
boundary scan. For detailed information on the TAP and
TAP controller, refer to IEEE Std 1149.1 “IEEE Standard
Test Access Port and Boundary-Scan Architecture” on
the IEEE website at www.standards.ieee.org.
Figure 10. JTAG Interface Block Diagram
P1.1/TMS
P1.3/TCK
P1.2/TDI
TO DEBUG
DVDDIO
DVDDIO
DVDDIO
______________________________________________________________________________________
ENGINE
POWER-ON
Ultrasonic Distance-Measuring System
RESET
WRITE
16-Bit, RISC, Microcontroller-Based,
READ
JTAG Interface
7 6 5
INSTRUCTION REGISTER
CONTROLLER
SYSTEM PROGRAMMING REGISTER
DEBUG REGISTER
SHADOW REGISTER
TAP
4 3 2
BYPASS
4 3 2
The TAP controller communicates synchronously with
the host system (bus master) through four digital I/Os:
test mode select (TMS), test clock (TCK), test data
input (TDI), and test data output (TDO). The internal
TAP module consists of shift registers and a TAP con-
troller (Figure 10). The shift registers serve as transmit
and receive data buffers for a debugger. Maintain the
maximum TCK clock frequency to below 1/8 the system
clock frequency for proper operation.
1 0 S1 S0
UPDATE-DR
UPDATE-DR
2
1 0
1 0
MAXQ7667
DVDDIO
P1.0/TDO
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