DS80C310-MCG+ Maxim Integrated Products, DS80C310-MCG+ Datasheet - Page 15
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DS80C310-MCG+
Manufacturer Part Number
DS80C310-MCG+
Description
IC MCU HI SPEED 25MHZ 40-DIP
Manufacturer
Maxim Integrated Products
Series
80Cr
Datasheet
1.DS80C310FCG.pdf
(22 pages)
Specifications of DS80C310-MCG+
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SIO, UART/USART
Peripherals
Brown-out Detect/Reset, POR
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
80C
Core
8051
Data Bus Width
8 bit
Program Memory Size
64 KB
Data Ram Size
64 KB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Controller Family/series
(8051) 8052
No. Of I/o's
32
Ram Memory Size
256Byte
Cpu Speed
25MHz
No. Of Timers
3
Embedded Interface Type
UART
Digital Ic Case Style
DIP
Rohs Compliant
Yes
Interface Type
UART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
EXTERNAL CLOCK CHARACTERISTICS
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
DEFINITION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following are description of the symbols.
t
A
C
D
H
L
I
P
Q
R
V
W
X
Z
Note 2:
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
Serial Port Clock Cycle
Time
Output Data Setup to
Clock Rising
Output Data Hold from
Clock Rising
Input Data Hold after
Clock Rising
Clock Rising Edge to
Input Data Valid
PARAMETER
Time
Address
Clock
Input Data
Logic Level High
Logic Level Low
Instruction
Output Data
Valid
No longer a valid logic level
Tri-State
PSEN
RD
WR
PARAMETER
Address is held in a weak latch until overdriven by external memory.
Signal
Signal
SYMBOL
t
t
t
t
t
QVXH
XHQX
XHDX
XHDV
XLXL
SYMBOL
SM2 = 0, 12 clocks per cycle
SM2 = 1, 4 clocks per cycle
SM2 = 0, 12 clocks per cycle
SM2 = 1, 4 clocks per cycle
SM2 = 0, 12 clocks per cycle
SM2 = 1, 4 clocks per cycle
SM2 = 0, 12 clocks per cycle
SM2 = 1, 4 clocks per cycle
SM2 = 0, 12 clocks per cycle
SM2 = 1, 4 clocks per cycle
t
t
t
t
CHCX
CLCX
CHCL
CLCL
CONDITIONS
15 of 22
MIN
10
10
MIN
TYP
12t
10t
11t
4t
3t
2t
3t
TYP
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MAX
5
5
MAX
DS80C310
UNITS
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns