MC908SR12MFAER Freescale Semiconductor, MC908SR12MFAER Datasheet - Page 307

• Manufacturer Part Number: MC908SR12MFAER
• Description: IC MCU 12K FLASH 4/8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908SR12MFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 31
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: MC908SR12MFAER; MC908SR12MFAERTR

17.7.5
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
MMIIC
Data Transmit Register (MMDTR)
Address:
MMTXBE — MMIIC Transmit Buffer Empty
MMRXBF — MMIIC Receive Buffer Full
When the MMIIC module is enabled, MMEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit
when:
Reset:
Read:
Write:
This flag indicates the status of the data transmit register (MMDTR).
When the CPU writes the data to the MMDTR, the MMTXBE flag will
be cleared. MMTXBE is set when MMDTR is emptied by a transfer of
its data to the output circuit. Reset sets this bit.
This flag indicates the status of the data receive register (MMDRR).
When the CPU reads the data from the MMDRR, the MMRXBF flag
will be cleared. MMRXBF is set when MMDRR is full by a transfer of
data from the input circuit to the MMDRR. Reset clears this bit.
•
•
1 = Data transmit register empty
0 = Data transmit register full
1 = Data receive register full
0 = Data receive register empty
the module detects a matched calling address (MMATCH = 1),
with the calling master requesting data (MMSRW = 1); or
the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
Figure 17-8. MMIIC Data Transmit Register (MMDTR)
MMTD7
$004C
Bit 7
Multi-Master IIC Interface (MMIIC)
0
MMTD6
6
0
MMTD5
5
0
MMTD4
4
0
MMTD3
3
0
Multi-Master IIC Interface (MMIIC)
MMTD2
2
0
MMIIC I/O Registers
MMTD1
1
0
Data Sheet
MMTD0
Bit 0
0
307